[llvm] [AMDGPU] Enable volatile and non-temporal for loads to LDS (PR #153244)

[Krzysztof Drewniak via llvm-commits]

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@@ -2783,7 +2783,8 @@ class AMDGPUGlobalLoadLDS :
      llvm_i32_ty,                       // imm offset (applied to both global and LDS address)
      llvm_i32_ty],                      // auxiliary data (imm, cachepolicy (bit 0 = sc0,
                                         //                                   bit 1 = sc1,
-                                        //                                   bit 4 = scc))
+                                        //                                   bit 4 = scc,
+                                        //                                   bit 31 = volatile (compiler implemented)))
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krzysz00 wrote:

Yeah ... should making a table of `aux` bits bi this PR?

https://github.com/llvm/llvm-project/pull/153244