[llvm] [AArch64][GISel] Use emitIntegerCompare instead of emitting SUBS directly every time (PR #153659)
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Thu Aug 14 13:36:16 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/153659
>From 1535e4e1f096295c7684ec60c530455fb37a8eaa Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 14 Aug 2025 15:43:57 -0400
Subject: [PATCH] [AArch64] Use emitIntegerCompare instead of emitting SUBS
directly every time
Also, pass the same operands to it as we do in SelDAG, same with emitFPCompare.
---
.../GISel/AArch64InstructionSelector.cpp | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index ee34a85a5b507..1818dc5d8177e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -4965,11 +4965,19 @@ MachineInstr *AArch64InstructionSelector::emitConjunctionRec(
// Produce a normal comparison if we are first in the chain
if (!CCOp) {
- auto Dst = MRI.cloneVirtualRegister(LHS);
- if (isa<GICmp>(Cmp))
- return emitSUBS(Dst, Cmp->getOperand(2), Cmp->getOperand(3), MIB);
- return emitFPCompare(Cmp->getOperand(2).getReg(),
- Cmp->getOperand(3).getReg(), MIB);
+ if (isa<GICmp>(Cmp)) {
+ auto &Pred = Cmp->getOperand(1);
+ MachineInstr *Ret = emitIntegerCompare(Cmp->getOperand(2),
+ Cmp->getOperand(3), Pred, MIB);
+
+ // Change OutCC in case emitIntegerCompare() changed it.
+ auto PredOp = static_cast<CmpInst::Predicate>(Pred.getPredicate());
+
+ OutCC = changeICMPPredToAArch64CC(
+ PredOp, Cmp->getOperand(3).getReg(), MIB.getMRI());
+ return Ret;
+ }
+ return emitFPCompare(LHS, RHS, MIB, CC);
}
// Otherwise produce a ccmp.
return emitConditionalComparison(LHS, RHS, CC, Predicate, OutCC, MIB);
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