[llvm] [AMDGPU][MC] GFX9 - allow op_sel in v_interp_p2_f16 (PR #150712)

[Jun Wang via llvm-commits]

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@@ -566,6 +566,36 @@ v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
 // NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
 // VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
 
+v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1]
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jwanggit86 wrote:

The latest commit tries to do this. That means encoding op_sel[0] in src0_modifier, op_sel[2] in src2_modifier. However, op_sel[1] has nowhere to go because the instruction has no src1. As a result, in the output op_sel[] would have 3 elements: src0, src2, and dst.

https://github.com/llvm/llvm-project/pull/150712