[llvm] [AArch64] Define constructive EXT_ZZI pseudo instruction (PR #152552)
Gaëtan Bossu via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 14 05:27:16 PDT 2025
https://github.com/gbossu updated https://github.com/llvm/llvm-project/pull/152552
>From 76b3377e8ed765af83da53e24c3209a60232690c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ga=C3=ABtan=20Bossu?= <gaetan.bossu at arm.com>
Date: Wed, 6 Aug 2025 08:59:15 +0000
Subject: [PATCH 1/3] [AArch64] Define constructive EXT_ZZI pseudo instruction
It will get expanded into MOVPRFX_ZZ and EXT_ZZI by the
AArch64ExpandPseudo pass. This instruction takes a single Z register as
input, as opposed to the existing destructive EXT_ZZI instruction.
Note this patch only defines the pseudo, it isn't used in any ISel
pattern yet. It will later be used for vector.extract.
---
.../AArch64/AArch64ExpandPseudoInsts.cpp | 10 +++
.../lib/Target/AArch64/AArch64InstrFormats.td | 7 ++-
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 3 +-
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 4 +-
llvm/lib/Target/AArch64/AArch64SchedA320.td | 2 +-
llvm/lib/Target/AArch64/AArch64SchedA510.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN3.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV1.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV2.td | 2 +-
llvm/lib/Target/AArch64/SVEInstrFormats.td | 12 +++-
.../AArch64/expand-constructive-zzi.mir | 61 +++++++++++++++++++
12 files changed, 97 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index d6a3d59b7ccfe..0d677840056f0 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -528,6 +528,10 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
UseRev = true;
}
break;
+ case AArch64::Destructive2xRegImmUnpred:
+ // EXT_ZZI_CONSTRUCTIVE Zd, Zs, Imm ==> EXT_ZZI Zds, Zds, Zds, Imm
+ std::tie(DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 1, 2);
+ break;
default:
llvm_unreachable("Unsupported Destructive Operand type");
}
@@ -548,6 +552,7 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
break;
case AArch64::DestructiveUnaryPassthru:
case AArch64::DestructiveBinaryImm:
+ case AArch64::Destructive2xRegImmUnpred:
DOPRegIsUnique = true;
break;
case AArch64::DestructiveTernaryCommWithRev:
@@ -674,6 +679,11 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
.add(MI.getOperand(SrcIdx))
.add(MI.getOperand(Src2Idx));
break;
+ case AArch64::Destructive2xRegImmUnpred:
+ DOP.addReg(MI.getOperand(DOPIdx).getReg(), DOPRegState)
+ .add(MI.getOperand(SrcIdx))
+ .add(MI.getOperand(Src2Idx));
+ break;
}
if (PRFX) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index b033f889fbf61..456b21a70e90f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -36,7 +36,12 @@ def DestructiveBinary : DestructiveInstTypeEnum<5>;
def DestructiveBinaryComm : DestructiveInstTypeEnum<6>;
def DestructiveBinaryCommWithRev : DestructiveInstTypeEnum<7>;
def DestructiveTernaryCommWithRev : DestructiveInstTypeEnum<8>;
-def DestructiveUnaryPassthru : DestructiveInstTypeEnum<9>;
+
+// 3 inputs unpredicated (reg1, reg2, imm).
+// Can be MOVPRFX'd iff reg1 == reg2.
+def Destructive2xRegImmUnpred : DestructiveInstTypeEnum<9>;
+
+def DestructiveUnaryPassthru : DestructiveInstTypeEnum<10>;
class FalseLanesEnum<bits<2> val> {
bits<2> Value = val;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 7c255da333e4b..b903cd90c1e73 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -820,7 +820,8 @@ enum DestructiveInstType {
DestructiveBinaryComm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x6),
DestructiveBinaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x7),
DestructiveTernaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x8),
- DestructiveUnaryPassthru = TSFLAG_DESTRUCTIVE_INST_TYPE(0x9),
+ Destructive2xRegImmUnpred = TSFLAG_DESTRUCTIVE_INST_TYPE(0x9),
+ DestructiveUnaryPassthru = TSFLAG_DESTRUCTIVE_INST_TYPE(0xa),
};
enum FalseLaneType {
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 0c4b4f4c3ed88..0fb6cf7b049a1 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1021,7 +1021,9 @@ let Predicates = [HasNonStreamingSVE_or_SME2p2] in {
let Predicates = [HasSVE_or_SME] in {
defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>;
defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
- defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext>;
+ defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext, "EXT_ZZI_CONSTRUCTIVE">;
+
+ def EXT_ZZI_CONSTRUCTIVE : UnpredRegImmPseudo<"EXT_ZZI_CONSTRUCTIVE", ZPR8, imm0_255>;
defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit", AArch64rbit_mt>;
defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb", AArch64revb_mt>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA320.td b/llvm/lib/Target/AArch64/AArch64SchedA320.td
index 89ed13389daf0..5ec95c707c28f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA320.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA320.td
@@ -847,7 +847,7 @@ def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^[SU]XTB_ZPmZ
"^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instrs EXT_ZZI, EXT_ZZI_B)>;
+def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;
// Extract narrow saturating
def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA510.td b/llvm/lib/Target/AArch64/AArch64SchedA510.td
index 9456878946151..b93d67f3091e7 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA510.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA510.td
@@ -825,7 +825,7 @@ def : InstRW<[CortexA510Write<3, CortexA510UnitVALU>], (instregex "^[SU]XTB_ZPmZ
"^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[CortexA510Write<3, CortexA510UnitVALU>], (instrs EXT_ZZI, EXT_ZZI_B)>;
+def : InstRW<[CortexA510Write<3, CortexA510UnitVALU>], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;
// Extract narrow saturating
def : InstRW<[CortexA510Write<4, CortexA510UnitVALU>], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index 91a707910a7f3..e7982226ff3d1 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -1785,7 +1785,7 @@ def : InstRW<[N2Write_2c_1V1], (instregex "^[SU]XTB_ZPmZ_[HSD]",
"^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[N2Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_B)>;
+def : InstRW<[N2Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;
// Extract narrow saturating
def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]$",
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
index ecfb1249cfc49..e44d40f8d7020 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
@@ -1757,7 +1757,7 @@ def : InstRW<[N3Write_2c_1V], (instregex "^[SU]XTB_ZPmZ_[HSD]",
"^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[N3Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_B)>;
+def : InstRW<[N3Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;
// Extract narrow saturating
def : InstRW<[N3Write_4c_1V1], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]$",
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 368665467859f..44625a2034d9d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -1575,7 +1575,7 @@ def : InstRW<[V1Write_2c_1V1], (instregex "^[SU]XTB_ZPmZ_[HSD]",
"^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[V1Write_2c_1V01], (instrs EXT_ZZI)>;
+def : InstRW<[V1Write_2c_1V01], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE)>;
// Extract/insert operation, SIMD and FP scalar form
def : InstRW<[V1Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$",
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index b2c3da03b4b84..6261220082029 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -2272,7 +2272,7 @@ def : InstRW<[V2Write_2c_1V13], (instregex "^[SU]XTB_ZPmZ_[HSD]",
"^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[V2Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_B)>;
+def : InstRW<[V2Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;
// Extract narrow saturating
def : InstRW<[V2Write_4c_1V13], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index a0320f919e8c5..3e291ef458161 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -809,6 +809,11 @@ let hasNoSchedulingInfo = 1 in {
Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
let FalseLanes = flags;
}
+
+ class UnpredRegImmPseudo<string name, ZPRRegOp zprty, Operand immty>
+ : SVEPseudo2Instr<name, 0>,
+ Pseudo<(outs zprty:$Zd), (ins zprty:$Zs, immty:$imm), []> {
+ }
}
//
@@ -1885,13 +1890,14 @@ class sve_int_perm_extract_i<string asm>
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
- let DestructiveInstType = DestructiveOther;
+ let DestructiveInstType = Destructive2xRegImmUnpred;
let ElementSize = ElementSizeNone;
let hasSideEffects = 0;
}
-multiclass sve_int_perm_extract_i<string asm, SDPatternOperator op> {
- def NAME : sve_int_perm_extract_i<asm>;
+multiclass sve_int_perm_extract_i<string asm, SDPatternOperator op, string pseudoInstrName> {
+ def NAME : sve_int_perm_extract_i<asm>,
+ SVEPseudo2Instr<pseudoInstrName, 1>;
def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i8, nxv16i8, i32, imm0_255,
!cast<Instruction>(NAME)>;
diff --git a/llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir b/llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir
new file mode 100644
index 0000000000000..a3f27dc40a88e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -mattr=+sve -run-pass=aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
+
+# Test the expansion of constructive binary operations into their
+# destructive counterparts.
+
+
+# EXT_ZZI_CONSTRUCTIVE
+
+---
+name: test_ext_zzi_unique
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_ext_zzi_unique
+ ; CHECK: BUNDLE implicit-def $z2, implicit-def $q2, implicit-def $d2, implicit-def $s2, implicit-def $h2, implicit-def $b2, implicit-def $b2_hi, implicit-def $h2_hi, implicit-def $s2_hi, implicit-def $d2_hi, implicit-def $q2_hi, implicit killed $z0 {
+ ; CHECK-NEXT: $z2 = MOVPRFX_ZZ $z0
+ ; CHECK-NEXT: $z2 = EXT_ZZI internal killed $z2, killed $z0, 1
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: RET undef $lr, implicit killed $z2
+ $z2 = EXT_ZZI_CONSTRUCTIVE killed $z0, 1
+ RET_ReallyLR implicit killed $z2
+...
+
+---
+name: test_ext_zzi_already_destructive
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_ext_zzi_already_destructive
+ ; CHECK: $z2 = EXT_ZZI killed $z2, killed $z2, 1
+ ; CHECK-NEXT: RET undef $lr, implicit killed $z2
+ $z2 = EXT_ZZI_CONSTRUCTIVE killed $z2, 1
+ RET_ReallyLR implicit killed $z2
+...
+
+---
+name: test_ext_zzi_unique_implicit_ops
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_ext_zzi_unique_implicit_ops
+ ; CHECK: BUNDLE implicit-def $z2, implicit-def $q2, implicit-def $d2, implicit-def $s2, implicit-def $h2, implicit-def $b2, implicit-def $b2_hi, implicit-def $h2_hi, implicit-def $s2_hi, implicit-def $d2_hi, implicit-def $q2_hi, implicit killed $z0, implicit killed $q0 {
+ ; CHECK-NEXT: $z2 = MOVPRFX_ZZ $z0, implicit killed $q0
+ ; CHECK-NEXT: $z2 = EXT_ZZI internal killed $z2, killed $z0, 1, implicit-def $q2
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: RET undef $lr, implicit killed $q2
+ $z2 = EXT_ZZI_CONSTRUCTIVE killed $z0, 1, implicit-def $q2, implicit killed $q0
+ RET_ReallyLR implicit killed $q2
+...
+
+---
+name: test_ext_zzi_undef
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_ext_zzi_undef
+ ; CHECK: BUNDLE implicit-def $z2, implicit-def $q2, implicit-def $d2, implicit-def $s2, implicit-def $h2, implicit-def $b2, implicit-def $b2_hi, implicit-def $h2_hi, implicit-def $s2_hi, implicit-def $d2_hi, implicit-def $q2_hi, implicit undef $z0 {
+ ; CHECK-NEXT: $z2 = MOVPRFX_ZZ undef $z0
+ ; CHECK-NEXT: $z2 = EXT_ZZI internal killed $z2, undef $z0, 1
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: RET undef $lr, implicit killed $z2
+ $z2 = EXT_ZZI_CONSTRUCTIVE undef $z0, 1
+ RET_ReallyLR implicit killed $z2
+...
>From 8a891a7ad54fab032abd7e2ed2086d928a6ad425 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ga=C3=ABtan=20Bossu?= <gaetan.bossu at arm.com>
Date: Wed, 13 Aug 2025 14:15:38 +0000
Subject: [PATCH 2/3] Address comments
- More consistent .td
- Clearer comment in AArch64ExpandPseudoInsts.cpp
---
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp | 3 ++-
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 +-
llvm/lib/Target/AArch64/SVEInstrFormats.td | 8 ++++----
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 0d677840056f0..1d27e2776cbaf 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -529,7 +529,8 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
}
break;
case AArch64::Destructive2xRegImmUnpred:
- // EXT_ZZI_CONSTRUCTIVE Zd, Zs, Imm ==> EXT_ZZI Zds, Zds, Zds, Imm
+ // EXT_ZZI_CONSTRUCTIVE Zd, Zs, Imm
+ // ==> MOVPRFX Zd Zs; EXT_ZZI Zd, Zd, Zs, Imm
std::tie(DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 1, 2);
break;
default:
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 0fb6cf7b049a1..9775238027650 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1023,7 +1023,7 @@ let Predicates = [HasSVE_or_SME] in {
defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext, "EXT_ZZI_CONSTRUCTIVE">;
- def EXT_ZZI_CONSTRUCTIVE : UnpredRegImmPseudo<"EXT_ZZI_CONSTRUCTIVE", ZPR8, imm0_255>;
+ def EXT_ZZI_CONSTRUCTIVE : UnpredRegImmPseudo<ZPR8, imm0_255>;
defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit", AArch64rbit_mt>;
defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb", AArch64revb_mt>;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 3e291ef458161..a3a7d0f74e1bc 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -810,8 +810,8 @@ let hasNoSchedulingInfo = 1 in {
let FalseLanes = flags;
}
- class UnpredRegImmPseudo<string name, ZPRRegOp zprty, Operand immty>
- : SVEPseudo2Instr<name, 0>,
+ class UnpredRegImmPseudo<ZPRRegOp zprty, Operand immty>
+ : SVEPseudo2Instr<NAME, 0>,
Pseudo<(outs zprty:$Zd), (ins zprty:$Zs, immty:$imm), []> {
}
}
@@ -1895,9 +1895,9 @@ class sve_int_perm_extract_i<string asm>
let hasSideEffects = 0;
}
-multiclass sve_int_perm_extract_i<string asm, SDPatternOperator op, string pseudoInstrName> {
+multiclass sve_int_perm_extract_i<string asm, SDPatternOperator op, string Ps> {
def NAME : sve_int_perm_extract_i<asm>,
- SVEPseudo2Instr<pseudoInstrName, 1>;
+ SVEPseudo2Instr<Ps, 1>;
def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i8, nxv16i8, i32, imm0_255,
!cast<Instruction>(NAME)>;
>From 3293d18439c1746aa9eccd73d0176683f0e9c602 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ga=C3=ABtan=20Bossu?= <gaetan.bossu at arm.com>
Date: Thu, 14 Aug 2025 12:24:22 +0000
Subject: [PATCH 3/3] Update test after rebase
Due to #142563
---
llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir b/llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir
index a3f27dc40a88e..55287712b12c3 100644
--- a/llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir
+++ b/llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir
@@ -12,7 +12,7 @@ name: test_ext_zzi_unique
body: |
bb.0:
; CHECK-LABEL: name: test_ext_zzi_unique
- ; CHECK: BUNDLE implicit-def $z2, implicit-def $q2, implicit-def $d2, implicit-def $s2, implicit-def $h2, implicit-def $b2, implicit-def $b2_hi, implicit-def $h2_hi, implicit-def $s2_hi, implicit-def $d2_hi, implicit-def $q2_hi, implicit killed $z0 {
+ ; CHECK: BUNDLE implicit-def $z2, implicit killed $z0 {
; CHECK-NEXT: $z2 = MOVPRFX_ZZ $z0
; CHECK-NEXT: $z2 = EXT_ZZI internal killed $z2, killed $z0, 1
; CHECK-NEXT: }
@@ -37,7 +37,7 @@ name: test_ext_zzi_unique_implicit_ops
body: |
bb.0:
; CHECK-LABEL: name: test_ext_zzi_unique_implicit_ops
- ; CHECK: BUNDLE implicit-def $z2, implicit-def $q2, implicit-def $d2, implicit-def $s2, implicit-def $h2, implicit-def $b2, implicit-def $b2_hi, implicit-def $h2_hi, implicit-def $s2_hi, implicit-def $d2_hi, implicit-def $q2_hi, implicit killed $z0, implicit killed $q0 {
+ ; CHECK: BUNDLE implicit-def $z2, implicit-def $q2, implicit killed $z0, implicit killed $q0 {
; CHECK-NEXT: $z2 = MOVPRFX_ZZ $z0, implicit killed $q0
; CHECK-NEXT: $z2 = EXT_ZZI internal killed $z2, killed $z0, 1, implicit-def $q2
; CHECK-NEXT: }
@@ -51,7 +51,7 @@ name: test_ext_zzi_undef
body: |
bb.0:
; CHECK-LABEL: name: test_ext_zzi_undef
- ; CHECK: BUNDLE implicit-def $z2, implicit-def $q2, implicit-def $d2, implicit-def $s2, implicit-def $h2, implicit-def $b2, implicit-def $b2_hi, implicit-def $h2_hi, implicit-def $s2_hi, implicit-def $d2_hi, implicit-def $q2_hi, implicit undef $z0 {
+ ; CHECK: BUNDLE implicit-def $z2, implicit undef $z0 {
; CHECK-NEXT: $z2 = MOVPRFX_ZZ undef $z0
; CHECK-NEXT: $z2 = EXT_ZZI internal killed $z2, undef $z0, 1
; CHECK-NEXT: }
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