[llvm] d92671c - [PhaseOrdering] Add tests for optimizing std::find for AArch64.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 14 03:26:48 PDT 2025
Author: Florian Hahn
Date: 2025-08-14T11:25:55+01:00
New Revision: d92671cf7dc316730e7bacba04b642e70059d640
URL: https://github.com/llvm/llvm-project/commit/d92671cf7dc316730e7bacba04b642e70059d640
DIFF: https://github.com/llvm/llvm-project/commit/d92671cf7dc316730e7bacba04b642e70059d640.diff
LOG: [PhaseOrdering] Add tests for optimizing std::find for AArch64.
Added:
llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
new file mode 100644
index 0000000000000..fa25af5f3467d
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
@@ -0,0 +1,130 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -O3 -S %s | FileCheck %s
+
+target triple = "arm64-apple-macosx15.0.0"
+
+define i64 @std_find_i16_constant_offset_with_assumptions(ptr %first.coerce, i16 noundef signext %s) nofree nosync {
+; CHECK-LABEL: define i64 @std_find_i16_constant_offset_with_assumptions(
+; CHECK-SAME: ptr [[FIRST_COERCE:%.*]], i16 noundef signext [[S:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[FIRST_COERCE]], i64 2) ]
+; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[FIRST_COERCE]], i64 256) ]
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[FIRST_COERCE]] to i64
+; CHECK-NEXT: [[COERCE_VAL_PI_I:%.*]] = add i64 [[TMP0]], 256
+; CHECK-NEXT: [[COERCE_VAL_IP:%.*]] = inttoptr i64 [[COERCE_VAL_PI_I]] to ptr
+; CHECK-NEXT: [[CMP_NOT6_I_I:%.*]] = icmp eq ptr [[FIRST_COERCE]], [[COERCE_VAL_IP]]
+; CHECK-NEXT: br i1 [[CMP_NOT6_I_I]], label %[[RETURN:.*]], label %[[LOOP_HEADER:.*]]
+; CHECK: [[LOOP_HEADER]]:
+; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ [[FIRST_COERCE]], %[[ENTRY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[PTR_IV]], align 2
+; CHECK-NEXT: [[CMP2_I_I:%.*]] = icmp eq i16 [[TMP1]], [[S]]
+; CHECK-NEXT: br i1 [[CMP2_I_I]], label %[[RETURN_LOOPEXIT:.*]], label %[[LOOP_LATCH]]
+; CHECK: [[LOOP_LATCH]]:
+; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds nuw i8, ptr [[PTR_IV]], i64 2
+; CHECK-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[COERCE_VAL_IP]]
+; CHECK-NEXT: br i1 [[CMP_NOT_I_I]], label %[[RETURN_LOOPEXIT]], label %[[LOOP_HEADER]]
+; CHECK: [[RETURN_LOOPEXIT]]:
+; CHECK-NEXT: [[MERGE_PH:%.*]] = phi ptr [ [[COERCE_VAL_IP]], %[[LOOP_LATCH]] ], [ [[PTR_IV]], %[[LOOP_HEADER]] ]
+; CHECK-NEXT: [[DOTPRE:%.*]] = ptrtoint ptr [[MERGE_PH]] to i64
+; CHECK-NEXT: br label %[[RETURN]]
+; CHECK: [[RETURN]]:
+; CHECK-NEXT: [[RES_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE]], %[[RETURN_LOOPEXIT]] ], [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: ret i64 [[RES_PRE_PHI]]
+;
+entry:
+ %first = alloca { ptr }, align 8
+ %s.addr = alloca i16, align 2
+ store ptr %first.coerce, ptr %first, align 8
+ store i16 %s, ptr %s.addr, align 2
+ %0 = load ptr, ptr %first, align 8
+ call void @llvm.assume(i1 true) [ "align"(ptr %0, i64 2) ]
+ call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %0, i64 256) ]
+ %start.ptr = load ptr, ptr %first, align 8
+ %1 = load i64, ptr %first, align 8
+ %coerce.val.pi.i = add i64 %1, 256
+ %coerce.val.ip = inttoptr i64 %coerce.val.pi.i to ptr
+ %cmp.not6.i.i = icmp eq ptr %start.ptr, %coerce.val.ip
+ br i1 %cmp.not6.i.i, label %return, label %loop.ph
+
+loop.ph:
+ %2 = load i16, ptr %s.addr, align 2
+ br label %loop.header
+
+loop.header:
+ %ptr.iv = phi ptr [ %start.ptr, %loop.ph ], [ %ptr.iv.next, %loop.latch ]
+ %3 = load i16, ptr %ptr.iv, align 2
+ %cmp2.i.i = icmp eq i16 %3, %2
+ br i1 %cmp2.i.i, label %return, label %loop.latch
+
+loop.latch:
+ %ptr.iv.next = getelementptr inbounds nuw i8, ptr %ptr.iv, i64 2
+ %cmp.not.i.i = icmp eq ptr %ptr.iv.next, %coerce.val.ip
+ br i1 %cmp.not.i.i, label %return, label %loop.header
+
+return:
+ %merge = phi ptr [ %start.ptr, %entry ], [ %coerce.val.ip, %loop.latch ], [ %ptr.iv, %loop.header ]
+ %res = ptrtoint ptr %merge to i64
+ ret i64 %res
+}
+
+define i64 @std_find_i16_constant_offset_no_assumptions(ptr %first.coerce, i16 noundef signext %s) nofree nosync {
+; CHECK-LABEL: define i64 @std_find_i16_constant_offset_no_assumptions(
+; CHECK-SAME: ptr [[FIRST_COERCE:%.*]], i16 noundef signext [[S:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[FIRST_COERCE]] to i64
+; CHECK-NEXT: [[COERCE_VAL_PI_I:%.*]] = add i64 [[TMP0]], 256
+; CHECK-NEXT: [[COERCE_VAL_IP:%.*]] = inttoptr i64 [[COERCE_VAL_PI_I]] to ptr
+; CHECK-NEXT: [[CMP_NOT6_I_I:%.*]] = icmp eq ptr [[FIRST_COERCE]], [[COERCE_VAL_IP]]
+; CHECK-NEXT: br i1 [[CMP_NOT6_I_I]], label %[[RETURN:.*]], label %[[LOOP_HEADER:.*]]
+; CHECK: [[LOOP_HEADER]]:
+; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ [[FIRST_COERCE]], %[[ENTRY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[PTR_IV]], align 2
+; CHECK-NEXT: [[CMP2_I_I:%.*]] = icmp eq i16 [[TMP1]], [[S]]
+; CHECK-NEXT: br i1 [[CMP2_I_I]], label %[[RETURN_LOOPEXIT:.*]], label %[[LOOP_LATCH]]
+; CHECK: [[LOOP_LATCH]]:
+; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds nuw i8, ptr [[PTR_IV]], i64 2
+; CHECK-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[COERCE_VAL_IP]]
+; CHECK-NEXT: br i1 [[CMP_NOT_I_I]], label %[[RETURN_LOOPEXIT]], label %[[LOOP_HEADER]]
+; CHECK: [[RETURN_LOOPEXIT]]:
+; CHECK-NEXT: [[MERGE_PH:%.*]] = phi ptr [ [[COERCE_VAL_IP]], %[[LOOP_LATCH]] ], [ [[PTR_IV]], %[[LOOP_HEADER]] ]
+; CHECK-NEXT: [[DOTPRE:%.*]] = ptrtoint ptr [[MERGE_PH]] to i64
+; CHECK-NEXT: br label %[[RETURN]]
+; CHECK: [[RETURN]]:
+; CHECK-NEXT: [[RES_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE]], %[[RETURN_LOOPEXIT]] ], [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: ret i64 [[RES_PRE_PHI]]
+;
+entry:
+ %first = alloca { ptr }, align 8
+ %s.addr = alloca i16, align 2
+ store ptr %first.coerce, ptr %first, align 8
+ store i16 %s, ptr %s.addr, align 2
+ %0 = load ptr, ptr %first, align 8
+ %start.ptr = load ptr, ptr %first, align 8
+ %1 = load i64, ptr %first, align 8
+ %coerce.val.pi.i = add i64 %1, 256
+ %coerce.val.ip = inttoptr i64 %coerce.val.pi.i to ptr
+ %cmp.not6.i.i = icmp eq ptr %start.ptr, %coerce.val.ip
+ br i1 %cmp.not6.i.i, label %return, label %loop.ph
+
+loop.ph:
+ %2 = load i16, ptr %s.addr, align 2
+ br label %loop.header
+
+loop.header:
+ %ptr.iv = phi ptr [ %start.ptr, %loop.ph ], [ %ptr.iv.next, %loop.latch ]
+ %3 = load i16, ptr %ptr.iv, align 2
+ %cmp2.i.i = icmp eq i16 %3, %2
+ br i1 %cmp2.i.i, label %return, label %loop.latch
+
+loop.latch:
+ %ptr.iv.next = getelementptr inbounds nuw i8, ptr %ptr.iv, i64 2
+ %cmp.not.i.i = icmp eq ptr %ptr.iv.next, %coerce.val.ip
+ br i1 %cmp.not.i.i, label %return, label %loop.header
+
+return:
+ %merge = phi ptr [ %start.ptr, %entry ], [ %coerce.val.ip, %loop.latch ], [ %ptr.iv, %loop.header ]
+ %res = ptrtoint ptr %merge to i64
+ ret i64 %res
+}
+
+declare void @llvm.assume(i1 noundef)
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