[llvm] [RISCV] Add initial assembler/MC layer support for big-endian (PR #146534)

[Djordje Todorovic via llvm-commits]

djtodoro wrote:

> Do we need to gate this behind -menable-experimental-extensions (or an equivalent given it's not really an extension)? There is no ABI specification for it yet and I would be concerned about future incompatibility. GCC implements _an_ ABI but IIRC there were concerns about whether it was actually a sensible ABI or organically came into being, possibly around things like structs passed in register pairs?

Hmm, the `-menable-experimental-extensions` may not be best match for what we need here, but I agree that it would be good to add something like that, how about something like:

```
$ git diff
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 12e4e813f5d9..1ca7d237328f 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -35,6 +35,7 @@
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Passes/PassBuilder.h"
 #include "llvm/Support/Compiler.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/IPO.h"
 #include "llvm/Transforms/Scalar.h"
@@ -209,6 +210,15 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
   setMachineOutliner(true);
   setSupportsDefaultOutlining(true);
 
+  // Emit warning for big-endian RISC-V targets as they are experimental
+  // and don't have an official ABI specification yet.
+  if (!TT.isLittleEndian()) {
+    errs() << "warning: RISC-V big-endian support is experimental and may "
+              "change in the future. There is no official ABI specification "
+              "yet, and the implementation may be incompatible with future "
+              "standards.\n";
+  }
+
   if (TT.isOSFuchsia() && !TT.isArch64Bit())
     report_fatal_error("Fuchsia is only supported for 64-bit");
 ```
 

https://github.com/llvm/llvm-project/pull/146534