[llvm] [SPIRV] Test files for SPV_INTEL_device_side_avc_motion_estimation,SPV_INTEL_fast_math_mode,SPV_KHR_bfloat16,SPV_KHR_untyped_pointers (PR #153549)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 14 00:37:23 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-spir-v
Author: Aadesh Premkumar (aadeshps-mcw)
<details>
<summary>Changes</summary>
--Added test for SPV_INTEL_device_side_avc_motion_estimation,SPV_INTEL_fast_math_mode,SPV_KHR_bfloat16,SPV_KHR_untyped_pointers extensions.
--Marked as Xfail, because they are not yet implemented.
---
Patch is 40.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/153549.diff
14 Files Affected:
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl (+152)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll.ll (+12)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll (+48)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll.ll (+86)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fast_math_mode/fp_contract_reassoc_fast_mode.ll (+35)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll (+20)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16_dot.ll (+22)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/cooperative_matrix_bfloat16.ll (+25)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/globals.ll (+48)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/infinite-phi.ll (+35)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/read_image.ll (+51)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/store.ll (+47)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_access_chain.ll (+26)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_type.ll (+24)
``````````diff
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
new file mode 100644
index 0000000000000..5dc1c98f23ac1
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
@@ -0,0 +1,152 @@
+; RUN: clang -cc1 -O1 -triple spirv64-unknown-unknown -cl-std=CL2.0 -finclude-default-header -emit-llvm %s -o %t.ll
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %t.ll -o - | FileCheck %s
+; XFAIL: *
+
+void foo(intel_sub_group_avc_ime_payload_t ime_payload,
+ intel_sub_group_avc_ime_result_single_reference_streamout_t sstreamout,
+ intel_sub_group_avc_ime_result_dual_reference_streamout_t dstreamout,
+ intel_sub_group_avc_ime_result_t ime_result,
+ intel_sub_group_avc_mce_result_t mce_result,
+ intel_sub_group_avc_ref_payload_t ref_payload,
+ intel_sub_group_avc_sic_payload_t sic_payload,
+ intel_sub_group_avc_sic_result_t sic_result,
+ intel_sub_group_avc_mce_payload_t mce_payload) {
+ intel_sub_group_avc_mce_get_default_inter_base_multi_reference_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_shape_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_intra_luma_shape_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_motion_vector_cost_table(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_direction_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_intra_luma_mode_penalty(0, 0);
+
+ intel_sub_group_avc_ime_initialize(0, 0, 0);
+ intel_sub_group_avc_ime_set_single_reference(0, 0, ime_payload);
+ intel_sub_group_avc_ime_set_dual_reference(0, 0, 0, ime_payload);
+ intel_sub_group_avc_ime_ref_window_size(0, 0);
+ intel_sub_group_avc_ime_ref_window_size(0, 0);
+ intel_sub_group_avc_ime_adjust_ref_offset(0, 0, 0, 0);
+ intel_sub_group_avc_ime_set_max_motion_vector_count(0, ime_payload);
+
+ intel_sub_group_avc_ime_get_single_reference_streamin(sstreamout);
+ intel_sub_group_avc_ime_get_dual_reference_streamin(dstreamout);
+ intel_sub_group_avc_ime_get_border_reached(0i, ime_result);
+ intel_sub_group_avc_ime_get_streamout_major_shape_distortions(sstreamout, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_distortions(dstreamout, 0, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_motion_vectors(sstreamout, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_motion_vectors(dstreamout, 0, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_reference_ids(sstreamout, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_reference_ids(dstreamout, 0, 0);
+
+ intel_sub_group_avc_ime_set_dual_reference(0, 0, 0, ime_payload);
+ intel_sub_group_avc_ime_set_weighted_sad(0, ime_payload);
+ intel_sub_group_avc_ime_set_early_search_termination_threshold(0, ime_payload);
+
+ intel_sub_group_avc_fme_initialize(0, 0, 0, 0, 0, 0, 0);
+ intel_sub_group_avc_bme_initialize(0, 0, 0, 0, 0, 0, 0, 0);
+ intel_sub_group_avc_ref_set_bidirectional_mix_disable(ref_payload);
+
+ intel_sub_group_avc_sic_initialize(0);
+ intel_sub_group_avc_sic_configure_ipe(0, 0, 0, 0, 0, 0, 0, sic_payload);
+ intel_sub_group_avc_sic_configure_ipe(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, sic_payload);
+ intel_sub_group_avc_sic_configure_skc(0, 0, 0, 0, 0, sic_payload);
+ intel_sub_group_avc_sic_set_skc_forward_transform_enable(0, sic_payload);
+ intel_sub_group_avc_sic_set_block_based_raw_skip_sad(0, sic_payload);
+ intel_sub_group_avc_sic_set_intra_luma_shape_penalty(0, sic_payload);
+ intel_sub_group_avc_sic_set_intra_luma_mode_cost_function(0, 0, 0,
+ sic_payload);
+ intel_sub_group_avc_sic_set_intra_chroma_mode_cost_function(0, sic_payload);
+ intel_sub_group_avc_sic_get_best_ipe_luma_distortion(sic_result);
+ intel_sub_group_avc_sic_get_motion_vector_mask(0, 0);
+
+ intel_sub_group_avc_mce_set_source_interlaced_field_polarity(0, mce_payload);
+ intel_sub_group_avc_mce_set_single_reference_interlaced_field_polarity(
+ 0, mce_payload);
+ intel_sub_group_avc_mce_set_dual_reference_interlaced_field_polarities(
+ 0, 0, mce_payload);
+ intel_sub_group_avc_mce_set_inter_base_multi_reference_penalty(0,
+ mce_payload);
+ intel_sub_group_avc_mce_set_inter_shape_penalty(0, mce_payload);
+ intel_sub_group_avc_mce_set_inter_direction_penalty(0, mce_payload);
+ intel_sub_group_avc_mce_set_motion_vector_cost_function(0, 0, 0, mce_payload);
+ intel_sub_group_avc_mce_get_inter_reference_interlaced_field_polarities(
+ 0, 0, mce_result);
+}
+
+CHECK-DAG: OpCapability Groups
+CHECK-DAG: OpCapability SubgroupAvcMotionEstimationINTEL
+CHECK-DAG: OpCapability SubgroupAvcMotionEstimationIntraINTEL
+CHECK-DAG: OpCapability SubgroupAvcMotionEstimationChromaINTEL
+CHECK-DAG: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+CHECK: %[[#ImePayloadTy:]] = OpTypeAvcImePayloadINTEL
+CHECK: %[[#ImeSRefOutTy:]] = OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+CHECK: %[[#ImeDRefOutTy:]] = OpTypeAvcImeResultDualReferenceStreamoutINTEL
+CHECK: %[[#ImeResultTy:]] = OpTypeAvcImeResultINTEL
+CHECK: %[[#MceResultTy:]] = OpTypeAvcMceResultINTEL
+CHECK: %[[#RefPayloadTy:]] = OpTypeAvcRefPayloadINTEL
+CHECK: %[[#SicPayloadTy:]] = OpTypeAvcSicPayloadINTEL
+CHECK: %[[#SicResultTy:]] = OpTypeAvcSicResultINTEL
+CHECK: %[[#McePayloadTy:]] = OpTypeAvcMcePayloadINTEL
+CHECK: %[[#ImeSRefInTy:]] = OpTypeAvcImeSingleReferenceStreaminINTEL
+CHECK: %[[#ImeDRefInTy:]] = OpTypeAvcImeDualReferenceStreaminINTEL
+
+CHECK: %[[#ImePayload:]] = OpFunctionParameter %[[#ImePayloadTy]]
+CHECK: %[[#ImeSRefOut:]] = OpFunctionParameter %[[#ImeSRefOutTy]]
+CHECK: %[[#ImeDRefOut:]] = OpFunctionParameter %[[#ImeDRefOutTy]]
+CHECK: %[[#ImeResult:]] = OpFunctionParameter %[[#ImeResultTy]]
+CHECK: %[[#MceResult:]] = OpFunctionParameter %[[#MceResultTy]]
+CHECK: %[[#RefPayload:]] = OpFunctionParameter %[[#RefPayloadTy]]
+CHECK: %[[#SicPayload:]] = OpFunctionParameter %[[#SicPayloadTy]]
+CHECK: %[[#SicResult:]] = OpFunctionParameter %[[#SicResultTy]]
+CHECK: %[[#McePayload:]] = OpFunctionParameter %[[#McePayloadTy]]
+
+CHECK: OpSubgroupAvcMceGetDefaultInterBaseMultiReferencePenaltyINTEL
+CHECK: OpSubgroupAvcMceGetDefaultInterShapePenaltyINTEL
+CHECK: OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL
+CHECK: OpSubgroupAvcMceGetDefaultInterMotionVectorCostTableINTEL
+CHECK: OpSubgroupAvcMceGetDefaultInterDirectionPenaltyINTEL
+CHECK: OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL
+
+CHECK: OpSubgroupAvcImeInitializeINTEL %[[#ImePayloadTy]]
+CHECK: OpSubgroupAvcImeSetSingleReferenceINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+CHECK: OpSubgroupAvcImeSetDualReferenceINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+CHECK: OpSubgroupAvcImeRefWindowSizeINTEL
+CHECK: OpSubgroupAvcImeRefWindowSizeINTEL
+CHECK: OpSubgroupAvcImeAdjustRefOffsetINTEL
+CHECK: OpSubgroupAvcImeSetMaxMotionVectorCountINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+CHECK: OpSubgroupAvcImeGetSingleReferenceStreaminINTEL %[[#ImeSRefInTy]]{{.*}}%[[#ImeSRefOut]]
+CHECK: OpSubgroupAvcImeGetDualReferenceStreaminINTEL %[[#ImeDRefInTy]]{{.*}}%[[#ImeDRefOut]]
+CHECK: OpSubgroupAvcImeGetBorderReachedINTEL {{.*}} %[[#ImeResult]]
+CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeDistortionsINTEL {{.*}} %[[#ImeSRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeDistortionsINTEL {{.*}} %[[#ImeDRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeMotionVectorsINTEL {{.*}} %[[#ImeSRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeMotionVectorsINTEL {{.*}} %[[#ImeDRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeReferenceIdsINTEL {{.*}} %[[#ImeSRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeReferenceIdsINTEL {{.*}} %[[#ImeDRefOut]]
+CHECK: OpSubgroupAvcImeSetDualReferenceINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+CHECK: OpSubgroupAvcImeSetWeightedSadINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+CHECK: OpSubgroupAvcImeSetEarlySearchTerminationThresholdINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+CHECK: OpSubgroupAvcFmeInitializeINTEL %[[#RefPayloadTy]]
+CHECK: OpSubgroupAvcBmeInitializeINTEL %[[#RefPayloadTy]]
+
+CHECK: OpSubgroupAvcRefSetBidirectionalMixDisableINTEL %[[#RefPayloadTy]]{{.*}}%[[#RefPayload]]
+
+CHECK: OpSubgroupAvcSicInitializeINTEL %[[#SicPayloadTy]]
+CHECK: OpSubgroupAvcSicConfigureIpeLumaINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicConfigureIpeLumaChromaINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicConfigureSkcINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetSkcForwardTransformEnableINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetBlockBasedRawSkipSadINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetIntraLumaShapePenaltyINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL {{.*}} %[[#SicResult]]
+CHECK: OpSubgroupAvcSicGetMotionVectorMaskINTEL
+
+CHECK: OpSubgroupAvcMceSetSourceInterlacedFieldPolarityINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetSingleReferenceInterlacedFieldPolarityINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetDualReferenceInterlacedFieldPolaritiesINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetInterShapePenaltyINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetInterDirectionPenaltyINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceGetInterReferenceInterlacedFieldPolaritiesINTEL {{.*}} %[[#MceResult]]
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll.ll
new file mode 100644
index 0000000000000..857de8d597653
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll.ll
@@ -0,0 +1,12 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+; XFAIL: *
+
+; CHECK: OpName %[[#Name:]] "_Z31intel_sub_group_avc_mce_ime_boo"
+; CHECK: %[[#]] = OpFunctionCall %[[#]] %[[#Name]]
+
+define spir_func void @foo() {
+entry:
+ call spir_func void @_Z31intel_sub_group_avc_mce_ime_boo()
+ ret void
+}
+declare spir_func void @_Z31intel_sub_group_avc_mce_ime_boo()
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
new file mode 100644
index 0000000000000..23ff84ed0e13e
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
@@ -0,0 +1,48 @@
+; RUN:llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+; XFAIL: *
+
+; CHECK: OpCapability Groups
+; CHECK: OpCapability SubgroupAvcMotionEstimationINTEL
+; CHECK: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+; CHECK: OpTypeAvcMcePayloadINTEL
+; CHECK: %[[#IME_PAYLOAD:]] = OpTypeAvcImePayloadINTEL
+; CHECK: %[[#REF_PAYLOAD:]] = OpTypeAvcRefPayloadINTEL
+; CHECK: %[[#SIC_PAYLOAD:]] = OpTypeAvcSicPayloadINTEL
+; CHECK: OpTypeAvcMceResultINTEL
+; CHECK: %[[#IME_RESULT:]] = OpTypeAvcImeResultINTEL
+; CHECK: %[[#REF_RESULT:]] = OpTypeAvcRefResultINTEL
+; CHECK: %[[#SIC_RESULT:]] = OpTypeAvcSicResultINTEL
+; CHECK: %[[#SSTREAMOUT:]] = OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+; CHECK: %[[#DSTREAMOUT:]] = OpTypeAvcImeResultDualReferenceStreamoutINTEL
+; CHECK: %[[#SSTREAMIN:]] = OpTypeAvcImeSingleReferenceStreaminINTEL
+; CHECK: %[[#DSTREAMIN:]] = OpTypeAvcImeDualReferenceStreaminINTEL
+
+define spir_func void @foo() {
+entry:
+ %payload_mce = alloca target("spirv.AvcMcePayloadINTEL"), align 4
+ %payload_ime = alloca target("spirv.AvcImePayloadINTEL"), align 4
+ %payload_ref = alloca target("spirv.AvcRefPayloadINTEL"), align 4
+ %payload_sic = alloca target("spirv.AvcSicPayloadINTEL"), align 4
+ %result_mce = alloca target("spirv.AvcMceResultINTEL"), align 4
+ %result_ime = alloca target("spirv.AvcImeResultINTEL"), align 4
+ %result_ref = alloca target("spirv.AvcRefResultINTEL"), align 4
+ %result_sic = alloca target("spirv.AvcSicResultINTEL"), align 4
+ %sstreamout = alloca target("spirv.AvcImeResultSingleReferenceStreamoutINTEL"), align 4
+ %dstreamout = alloca target("spirv.AvcImeResultDualReferenceStreamoutINTEL"), align 4
+ %sstreamin = alloca target("spirv.AvcImeSingleReferenceStreaminINTEL"), align 4
+ %dstreamin = alloca target("spirv.AvcImeDualReferenceStreaminINTEL"), align 4
+ store target("spirv.AvcMcePayloadINTEL") zeroinitializer, ptr %payload_mce, align 4
+ store target("spirv.AvcImePayloadINTEL") zeroinitializer, ptr %payload_ime, align 4
+ store target("spirv.AvcRefPayloadINTEL") zeroinitializer, ptr %payload_ref, align 4
+ store target("spirv.AvcSicPayloadINTEL") zeroinitializer, ptr %payload_sic, align 4
+ store target("spirv.AvcMceResultINTEL") zeroinitializer, ptr %result_mce, align 4
+ store target("spirv.AvcImeResultINTEL") zeroinitializer, ptr %result_ime, align 4
+ store target("spirv.AvcRefResultINTEL") zeroinitializer, ptr %result_ref, align 4
+ store target("spirv.AvcSicResultINTEL") zeroinitializer, ptr %result_sic, align 4
+ store target("spirv.AvcImeResultSingleReferenceStreamoutINTEL") zeroinitializer, ptr %sstreamout, align 4
+ store target("spirv.AvcImeResultDualReferenceStreamoutINTEL") zeroinitializer, ptr %dstreamout, align 4
+ store target("spirv.AvcImeSingleReferenceStreaminINTEL") zeroinitializer, ptr %sstreamin, align 4
+ store target("spirv.AvcImeDualReferenceStreaminINTEL") zeroinitializer, ptr %dstreamin, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll.ll
new file mode 100644
index 0000000000000..2ee4d4731c5e4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll.ll
@@ -0,0 +1,86 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+; XFAIL: *
+
+; CHECK: OpCapability Groups
+; CHECK: OpCapability SubgroupAvcMotionEstimationINTEL
+; CHECK: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+; CHECK-DAG: %[[#ImePayloadTy:]] = OpTypeAvcImePayloadINTEL
+; CHECK-DAG: %[[#ImeResultTy:]] = OpTypeAvcImeResultINTEL
+; CHECK-DAG: %[[#RefPayloadTy:]] = OpTypeAvcRefPayloadINTEL
+; CHECK-DAG: %[[#RefResultTy:]] = OpTypeAvcRefResultINTEL
+; CHECK-DAG: %[[#SicPayloadTy:]] = OpTypeAvcSicPayloadINTEL
+; CHECK-DAG: %[[#SicResultTy:]] = OpTypeAvcSicResultINTEL
+; CHECK-DAG: %[[#McePayloadTy:]] = OpTypeAvcMcePayloadINTEL
+; CHECK-DAG: %[[#MceResultTy:]] = OpTypeAvcMceResultINTEL
+
+define spir_func void @test() #0 {
+entry:
+ %ime_payload = alloca target("spirv.AvcImePayloadINTEL"), align 8
+ %ime_result = alloca target("spirv.AvcImeResultINTEL"), align 8
+ %ref_payload = alloca target("spirv.AvcRefPayloadINTEL"), align 8
+ %ref_result = alloca target("spirv.AvcRefResultINTEL"), align 8
+ %sic_payload = alloca target("spirv.AvcSicPayloadINTEL"), align 8
+ %sic_result = alloca target("spirv.AvcSicResultINTEL"), align 8
+
+; CHECK: %[[#ImePayload:]] = OpLoad %[[#ImePayloadTy]]
+; CHECK: %[[#ImeResult:]] = OpLoad %[[#ImeResultTy]]
+; CHECK: %[[#RefPayload:]] = OpLoad %[[#RefPayloadTy]]
+; CHECK: %[[#RefResult:]] = OpLoad %[[#RefResultTy]]
+; CHECK: %[[#SicPayload:]] = OpLoad %[[#SicPayloadTy]]
+; CHECK: %[[#SicResult:]] = OpLoad %[[#SicResultTy]]
+
+ %0 = load target("spirv.AvcImePayloadINTEL"), target("spirv.AvcImePayloadINTEL")* %ime_payload, align 8
+ %1 = load target("spirv.AvcImeResultINTEL"), target("spirv.AvcImeResultINTEL")* %ime_result, align 8
+ %2 = load target("spirv.AvcRefPayloadINTEL"), target("spirv.AvcRefPayloadINTEL")* %ref_payload, align 8
+ %3 = load target("spirv.AvcRefResultINTEL"), target("spirv.AvcRefResultINTEL")* %ref_result, align 8
+ %4 = load target("spirv.AvcSicPayloadINTEL"), target("spirv.AvcSicPayloadINTEL")* %sic_payload, align 8
+ %5 = load target("spirv.AvcSicResultINTEL"), target("spirv.AvcSicResultINTEL")* %sic_result, align 8
+
+; CHECK: %[[#ImeMcePayloadConv:]] = OpSubgroupAvcImeConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#ImePayload]]
+; CHECK: %[[#McePayloadRet0:]] = OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#ImeMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToImePayloadINTEL
+; CHECK-SAME: %[[#ImePayloadTy]] %[[#McePayloadRet0]]
+ %call0 = call spir_func target("spirv.AvcImePayloadINTEL") @_Z62intel_sub_group_avc_ime_set_inter_base_multi_reference_penaltyh37ocl_intel_sub_group_avc_ime_payload_t(i8 zeroext 0, target("spirv.AvcImePayloadINTEL") %0) #2
+
+; CHECK: %[[#ImeMceResultConv:]] = OpSubgroupAvcImeConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#ImeResult]]
+; CHECK: OpSubgroupAvcMceGetMotionVectorsINTEL {{.*}} %[[#ImeMceResultConv]]
+ %call1 = call spir_func i64 @_Z42intel_sub_group_avc_ime_get_motion_vectors36ocl_intel_sub_group_avc_ime_result_t(target("spirv.AvcImeResultINTEL") %1) #2
+
+; CHECK: %[[#RefMcePayloadConv:]] = OpSubgroupAvcRefConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#RefPayload]]
+; CHECK: %[[#McePayloadRet1:]] = OpSubgroupAvcMceSetInterShapePenaltyINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#RefMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToRefPayloadINTEL
+; CHECK-SAME: %[[#RefPayloadTy]] %[[#McePayloadRet1]]
+ %call2 = call spir_func target("spirv.AvcRefPayloadINTEL") @_Z47intel_sub_group_avc_ref_set_inter_shape_penaltym37ocl_intel_sub_group_avc_ref_payload_t(i64 0, target("spirv.AvcRefPayloadINTEL") %2) #2
+
+; CHECK: %[[#RefMceResultConv:]] = OpSubgroupAvcRefConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#RefResult]]
+; CHECK: OpSubgroupAvcMceGetInterDistortionsINTEL {{.*}} %[[#RefMceResultConv]]
+ %call3 = call spir_func zeroext i16 @_Z45intel_sub_group_avc_ref_get_inter_distortions36ocl_intel_sub_group_avc_ref_result_t(target("spirv.AvcRefResultINTEL") %3) #2
+
+; CHECK: %[[#SicMcePayloadConv:]] = OpSubgroupAvcSicConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#SicPayload]]
+; CHECK: %[[#McePayloadRet2:]] = OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#SicMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToSicPayloadINTEL
+; CHECK-SAME: %[[#SicPayloadTy]] %[[#McePayloadRet2]]
+ %call4 = call spir_func target("spirv.AvcSicPayloadINTEL") @_Z55intel_sub_group_avc_sic_set_motion_vector_cost_functionmDv2_jh37ocl_intel_sub_group_avc_sic_payload_t(i64 0, <2 x i32> zeroinitializer, i8 zeroext 0, target("spirv.AvcSicPayloadINTEL") %4) #2
+
+; CHECK: %[[#SicMceResultConv:]] = OpSubgroupAvcSicConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#SicResult]]
+; CHECK: OpSubgroupAvcMceGetInterDistortionsINTEL {{.*}} %[[#SicMceResultConv]]
+ %call5 = call spir_func zeroext i16 @_Z45intel_sub_group_avc_sic_get_...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/153549
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