[llvm] [GISel] Fix crash in GlobalISel utils method (PR #153334)
Victor Mustya via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 13 15:20:38 PDT 2025
https://github.com/vmustya updated https://github.com/llvm/llvm-project/pull/153334
>From 9c20890f661994a95eb7b7e7418d96b2bf57e20a Mon Sep 17 00:00:00 2001
From: Victor Mustya <victor.mustya at intel.com>
Date: Tue, 12 Aug 2025 18:41:00 -0700
Subject: [PATCH 1/2] [GISel] Fix crash in GlobalISel utils method
The `getDefSrcRegIgnoringCopies` method in GlobalISel Utils crashed when
the first operand of the input instruction was not a register, e.g.,
the `INLINEASM` instruction has a non-register first operand.
---
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 5 ++-
.../regbankcombiner-inlineasm-crash.mir | 40 +++++++++++++++++++
2 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-inlineasm-crash.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 8955dd0370539..c6822f32d01b7 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -467,7 +467,10 @@ std::optional<DefinitionAndSourceRegister>
llvm::getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) {
Register DefSrcReg = Reg;
auto *DefMI = MRI.getVRegDef(Reg);
- auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
+ auto &Opnd = DefMI->getOperand(0);
+ if (!Opnd.isReg())
+ return DefinitionAndSourceRegister{DefMI, DefSrcReg};
+ auto DstTy = MRI.getType(Opnd.getReg());
if (!DstTy.isValid())
return std::nullopt;
unsigned Opc = DefMI->getOpcode();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-inlineasm-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-inlineasm-crash.mir
new file mode 100644
index 0000000000000..4bff92314c07b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-inlineasm-crash.mir
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+# COM: Check that the pass doesn't crash.
+
+---
+name: test_fmed3
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo:
+ mode:
+ ieee: true
+ dx10-clamp: true
+body: |
+ bb.1 :
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_fmed3
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %5(s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], %5, [[COPY2]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+ %0:vgpr(s32) = COPY $vgpr0
+ %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
+ %8:vgpr(s32) = COPY %2(s32)
+ %3:vgpr(s32) = G_FMUL %0, %8
+ %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
+ INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %5:vgpr_32
+ %10:vgpr(s32) = COPY %6(s32)
+ %4:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %5(s32), %10(s32)
+ $vgpr0 = COPY %4(s32)
+...
>From 15bc48bed6ae3ec482e3c655a1859bdda8440772 Mon Sep 17 00:00:00 2001
From: Victor Mustya <victor.mustya at intel.com>
Date: Wed, 13 Aug 2025 15:20:24 -0700
Subject: [PATCH 2/2] Re-implement the fix to take care of other cases, not
only the inline asm
---
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 12 +--
.../regbankcombiner-ignore-copies-crash.mir | 77 +++++++++++++++++++
.../regbankcombiner-inlineasm-crash.mir | 40 ----------
3 files changed, 84 insertions(+), 45 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-inlineasm-crash.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index c6822f32d01b7..3a0c7911f4cde 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -466,11 +466,13 @@ llvm::getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI) {
std::optional<DefinitionAndSourceRegister>
llvm::getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) {
Register DefSrcReg = Reg;
- auto *DefMI = MRI.getVRegDef(Reg);
- auto &Opnd = DefMI->getOperand(0);
- if (!Opnd.isReg())
- return DefinitionAndSourceRegister{DefMI, DefSrcReg};
- auto DstTy = MRI.getType(Opnd.getReg());
+ // This assumes that the code is in SSA form, so there should only be one
+ // definition.
+ if (MRI.def_empty(Reg))
+ return std::nullopt;
+ MachineOperand &DefOpnd = *MRI.def_begin(Reg);
+ MachineInstr *DefMI = DefOpnd.getParent();
+ auto DstTy = MRI.getType(DefOpnd.getReg());
if (!DstTy.isValid())
return std::nullopt;
unsigned Opc = DefMI->getOpcode();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
new file mode 100644
index 0000000000000..75f0061625599
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s
+
+# COM: Check that the pass doesn't crash.
+
+---
+name: test_inline_asm
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo:
+ mode:
+ ieee: true
+ dx10-clamp: true
+body: |
+ bb.1 :
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_inline_asm
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %5(s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], %5, [[COPY2]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = G_FCONSTANT float 2.000000e+00
+ %2:vgpr(s32) = COPY %1(s32)
+ %3:vgpr(s32) = G_FMUL %0, %2
+ %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
+ INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %5:vgpr_32
+ %6:vgpr(s32) = COPY %4(s32)
+ %7:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %5(s32), %6(s32)
+ $vgpr0 = COPY %7(s32)
+...
+
+---
+name: test_unmerge_values
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo:
+ mode:
+ ieee: true
+ dx10-clamp: true
+body: |
+ bb.1 :
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_unmerge_values
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], [[C2]], [[COPY2]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[C2]](s32)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = G_FCONSTANT float 2.000000e+00
+ %2:vgpr(s32) = COPY %1(s32)
+ %3:vgpr(s32) = G_FMUL %0, %2
+ %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
+ %5:vgpr(s64) = G_CONSTANT i64 123456789
+ %6:vgpr(s32), %7:vgpr(s32) = G_UNMERGE_VALUES %5(s64)
+ %8:vgpr(s32) = COPY %4(s32)
+ %9:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %7(s32), %8(s32)
+ $vgpr0 = COPY %7(s32)
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-inlineasm-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-inlineasm-crash.mir
deleted file mode 100644
index 4bff92314c07b..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-inlineasm-crash.mir
+++ /dev/null
@@ -1,40 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
-
-# COM: Check that the pass doesn't crash.
-
----
-name: test_fmed3
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-machineFunctionInfo:
- mode:
- ieee: true
- dx10-clamp: true
-body: |
- bb.1 :
- liveins: $vgpr0
-
- ; CHECK-LABEL: name: test_fmed3
- ; CHECK: liveins: $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %5(s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], %5, [[COPY2]]
- ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
- %0:vgpr(s32) = COPY $vgpr0
- %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
- %8:vgpr(s32) = COPY %2(s32)
- %3:vgpr(s32) = G_FMUL %0, %8
- %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
- INLINEASM &"v_mov_b32 $0, 0", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %5:vgpr_32
- %10:vgpr(s32) = COPY %6(s32)
- %4:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %5(s32), %10(s32)
- $vgpr0 = COPY %4(s32)
-...
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