[llvm] 9b93ccb - [RISCV] Fix Immediate Check for Xqcibi UGT (#153141)

[via llvm-commits]

Author: Sam Elliott
Date: 2025-08-12T11:06:00-07:00
New Revision: 9b93ccbcbe34750136a06eef4dd23a59d42fe99e

URL: https://github.com/llvm/llvm-project/commit/9b93ccbcbe34750136a06eef4dd23a59d42fe99e
DIFF: https://github.com/llvm/llvm-project/commit/9b93ccbcbe34750136a06eef4dd23a59d42fe99e.diff

LOG: [RISCV] Fix Immediate Check for Xqcibi UGT (#153141)

The check should be about unsigned 16-bit immediates, not signed ones.

This is not a bug per-se, as the old codegen was correct for the
uint16_max case, it just didn't end up using `qc.e.bgeui`, which we
would prefer it did.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/xqcibi.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e63b9374ebe25..aaa68517ccc1c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2523,11 +2523,10 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
       }
       break;
     case ISD::SETUGT:
-      if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isInt<16>(C + 1) &&
-          C != -1) {
+      if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isUInt<16>(C + 1)) {
         // We have a branch immediate instruction for SETUGE but not SETUGT.
         // Convert X > C to X >= C + 1, if (C + 1) is a 16-bit signed immediate.
-        RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType());
+        RHS = DAG.getConstant(C + 1, DL, RHS.getValueType());
         CC = ISD::SETUGE;
         return;
       }

diff  --git a/llvm/test/CodeGen/RISCV/xqcibi.ll b/llvm/test/CodeGen/RISCV/xqcibi.ll
index f628e0086374c..518ada6c9e631 100644
--- a/llvm/test/CodeGen/RISCV/xqcibi.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibi.ll
@@ -329,7 +329,8 @@ t:
 define i32 @bgeuimm16(i32 %a) {
 ; RV32I-LABEL: bgeuimm16:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    li a1, 99
+; RV32I-NEXT:    lui a1, 16
+; RV32I-NEXT:    addi a1, a1, -2
 ; RV32I-NEXT:    bltu a1, a0, .LBB11_2
 ; RV32I-NEXT:  # %bb.1: # %f
 ; RV32I-NEXT:    li a0, 0
@@ -340,14 +341,14 @@ define i32 @bgeuimm16(i32 %a) {
 ;
 ; RV32IXQCIBI-LABEL: bgeuimm16:
 ; RV32IXQCIBI:       # %bb.0:
-; RV32IXQCIBI-NEXT:    qc.e.bgeui a0, 100, .LBB11_2
+; RV32IXQCIBI-NEXT:    qc.e.bgeui a0, 65535, .LBB11_2
 ; RV32IXQCIBI-NEXT:  # %bb.1: # %f
 ; RV32IXQCIBI-NEXT:    li a0, 0
 ; RV32IXQCIBI-NEXT:    ret
 ; RV32IXQCIBI-NEXT:  .LBB11_2: # %t
 ; RV32IXQCIBI-NEXT:    li a0, 1
 ; RV32IXQCIBI-NEXT:    ret
-  %1 = icmp uge i32 %a, 100
+  %1 = icmp uge i32 %a, 65535
   br i1 %1, label %t, label %f, !prof !0
 f:
   ret i32 0