[llvm] b09b05a - [M68k] Fix incorrect boolean content type (#152572)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 12 08:46:44 PDT 2025
Author: Dan Salvato
Date: 2025-08-12T08:46:41-07:00
New Revision: b09b05a83ef781da8a967702488d10d4e5e6216d
URL: https://github.com/llvm/llvm-project/commit/b09b05a83ef781da8a967702488d10d4e5e6216d
DIFF: https://github.com/llvm/llvm-project/commit/b09b05a83ef781da8a967702488d10d4e5e6216d.diff
LOG: [M68k] Fix incorrect boolean content type (#152572)
M68k's SETCC instruction (`scc`) distinctly fills the destination byte
with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`,
LLVM can mistakenly think the destination holds `0x01` instead of `0xff`
and emit broken code as a result. This change corrects the boolean
content type to `ZeroOrNegativeOneBooleanContent`.
For example, this IR:
```llvm
define dso_local signext range(i8 0, 2) i8 @testBool(i32 noundef %a) local_unnamed_addr #0 {
entry:
%cmp = icmp eq i32 %a, 4660
%. = zext i1 %cmp to i8
ret i8 %.
}
```
would previously build as:
```asm
testBool: ; @testBool
cmpi.l #4660, (4,%sp)
seq %d0
and.l #255, %d0
rts
```
Notice the `zext` is erroneously not clearing the low bits, and thus the
register returns with 255 instead of 1. This patch fixes the issue:
```asm
testBool: ; @testBool
cmpi.l #4660, (4,%sp)
seq %d0
and.l #1, %d0
rts
```
Most of the tests containing `scc` suffered from the same value error as
described above, so those tests have been updated to match the new
output (which also logically corrects them).
Added:
Modified:
llvm/lib/Target/M68k/M68kISelLowering.cpp
llvm/lib/Target/M68k/M68kInstrArithmetic.td
llvm/test/CodeGen/M68k/Arith/add.ll
llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
llvm/test/CodeGen/M68k/Atomics/rmw.ll
llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
llvm/test/CodeGen/M68k/Control/cmp.ll
llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
llvm/test/CodeGen/M68k/Control/setcc.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 594ea9f48c201..c1a88bd796bee 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -51,7 +51,9 @@ M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
MVT PtrVT = MVT::i32;
- setBooleanContents(ZeroOrOneBooleanContent);
+ // This is based on M68k SetCC (scc) setting the destination byte to all 1s.
+ // See also getSetCCResultType().
+ setBooleanContents(ZeroOrNegativeOneBooleanContent);
auto *RegInfo = Subtarget.getRegisterInfo();
setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
diff --git a/llvm/lib/Target/M68k/M68kInstrArithmetic.td b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
index e2d4e49ddf27b..56b71db2d1d2f 100644
--- a/llvm/lib/Target/M68k/M68kInstrArithmetic.td
+++ b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
@@ -835,7 +835,7 @@ def : Pat<(MxSub 0, i8 :$src), (NEG8d MxDRD8 :$src)>;
def : Pat<(MxSub 0, i16:$src), (NEG16d MxDRD16:$src)>;
def : Pat<(MxSub 0, i32:$src), (NEG32d MxDRD32:$src)>;
// SExt of i1 values.
-// Although we specify `ZeroOrOneBooleanContent` for boolean content,
+// Although we specify `ZeroOrNegativeOneBooleanContent` for boolean content,
// we're still adding an AND here as we don't know the origin of the i1 value.
def : Pat<(sext_inreg i8:$src, i1), (NEG8d (AND8di MxDRD8:$src, 1))>;
def : Pat<(sext_inreg i16:$src, i1), (NEG16d (AND16di MxDRD16:$src, 1))>;
diff --git a/llvm/test/CodeGen/M68k/Arith/add.ll b/llvm/test/CodeGen/M68k/Arith/add.ll
index 417fe8f068479..73220c6eaf43e 100644
--- a/llvm/test/CodeGen/M68k/Arith/add.ll
+++ b/llvm/test/CodeGen/M68k/Arith/add.ll
@@ -85,9 +85,9 @@ define fastcc i32 @test9(i32 %x, i32 %y) nounwind readnone {
; CHECK: ; %bb.0:
; CHECK-NEXT: sub.l #10, %d0
; CHECK-NEXT: seq %d0
-; CHECK-NEXT: and.l #255, %d0
-; CHECK-NEXT: sub.l %d0, %d1
-; CHECK-NEXT: move.l %d1, %d0
+; CHECK-NEXT: ext.w %d0
+; CHECK-NEXT: ext.l %d0
+; CHECK-NEXT: add.l %d1, %d0
; CHECK-NEXT: rts
%cmp = icmp eq i32 %x, 10
%sub = sext i1 %cmp to i32
diff --git a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
index 423431750f20a..ad6843b310f06 100644
--- a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
@@ -102,8 +102,9 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: suba.l #12, %sp
; CHECK-NEXT: muls.l %d1, %d0
; CHECK-NEXT: svs %d1
-; CHECK-NEXT: sub.b #1, %d1
-; CHECK-NEXT: bne .LBB4_2
+; CHECK-NEXT: and.b #1, %d1
+; CHECK-NEXT: cmpi.b #0, %d1
+; CHECK-NEXT: beq .LBB4_2
; CHECK-NEXT: ; %bb.1: ; %overflow
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
diff --git a/llvm/test/CodeGen/M68k/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
index a277b8fe72ae4..71ab4326cfe7d 100644
--- a/llvm/test/CodeGen/M68k/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
@@ -37,9 +37,10 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: move.b %d0, %d3
; ATOMIC-NEXT: sub.b %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.b %d0, %d2
-; ATOMIC-NEXT: bne .LBB0_1
+; ATOMIC-NEXT: beq .LBB0_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -80,9 +81,10 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: move.w %d0, %d3
; ATOMIC-NEXT: sub.w %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.w %d0, %d2
-; ATOMIC-NEXT: bne .LBB1_1
+; ATOMIC-NEXT: beq .LBB1_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -121,9 +123,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: move.l %d0, %d3
; ATOMIC-NEXT: sub.l %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.l %d0, %d2
-; ATOMIC-NEXT: bne .LBB2_1
+; ATOMIC-NEXT: beq .LBB2_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -194,9 +197,10 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: move.b %d0, %d3
; ATOMIC-NEXT: sub.b %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.b %d0, %d2
-; ATOMIC-NEXT: bne .LBB4_1
+; ATOMIC-NEXT: beq .LBB4_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -242,9 +246,10 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: move.w %d1, %d3
; ATOMIC-NEXT: sub.w %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.w %d1, %d2
-; ATOMIC-NEXT: bne .LBB5_1
+; ATOMIC-NEXT: beq .LBB5_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -282,9 +287,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: move.l %d0, %d3
; ATOMIC-NEXT: sub.l %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.l %d0, %d2
-; ATOMIC-NEXT: beq .LBB6_4
+; ATOMIC-NEXT: bne .LBB6_4
; ATOMIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d2, %d0
@@ -434,9 +440,10 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: move.b %d0, %d3
; ATOMIC-NEXT: sub.b %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.b %d0, %d2
-; ATOMIC-NEXT: beq .LBB8_4
+; ATOMIC-NEXT: bne .LBB8_4
; ATOMIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.b %d2, %d0
@@ -486,9 +493,10 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: move.w %d0, %d3
; ATOMIC-NEXT: sub.w %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.w %d0, %d2
-; ATOMIC-NEXT: beq .LBB9_4
+; ATOMIC-NEXT: bne .LBB9_4
; ATOMIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.w %d2, %d0
@@ -537,9 +545,10 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: move.w %d0, %d3
; ATOMIC-NEXT: sub.w %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.w %d0, %d2
-; ATOMIC-NEXT: bne .LBB10_1
+; ATOMIC-NEXT: beq .LBB10_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -577,9 +586,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: move.l %d0, %d3
; ATOMIC-NEXT: sub.l %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.l %d0, %d2
-; ATOMIC-NEXT: bne .LBB11_1
+; ATOMIC-NEXT: beq .LBB11_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -622,9 +632,10 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-NEXT: move.b %d0, %d2
; ATOMIC-NEXT: sub.b %d1, %d2
; ATOMIC-NEXT: seq %d1
-; ATOMIC-NEXT: sub.b #1, %d1
+; ATOMIC-NEXT: and.b #1, %d1
+; ATOMIC-NEXT: cmpi.b #0, %d1
; ATOMIC-NEXT: move.b %d0, %d1
-; ATOMIC-NEXT: bne .LBB12_1
+; ATOMIC-NEXT: beq .LBB12_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
@@ -669,9 +680,10 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-NEXT: move.w %d0, %d2
; ATOMIC-NEXT: sub.w %d1, %d2
; ATOMIC-NEXT: seq %d1
-; ATOMIC-NEXT: sub.b #1, %d1
+; ATOMIC-NEXT: and.b #1, %d1
+; ATOMIC-NEXT: cmpi.b #0, %d1
; ATOMIC-NEXT: move.w %d0, %d1
-; ATOMIC-NEXT: bne .LBB13_1
+; ATOMIC-NEXT: beq .LBB13_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
@@ -716,9 +728,10 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-NEXT: move.l %d0, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
; ATOMIC-NEXT: seq %d1
-; ATOMIC-NEXT: sub.b #1, %d1
+; ATOMIC-NEXT: and.b #1, %d1
+; ATOMIC-NEXT: cmpi.b #0, %d1
; ATOMIC-NEXT: move.l %d0, %d1
-; ATOMIC-NEXT: bne .LBB14_1
+; ATOMIC-NEXT: beq .LBB14_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
diff --git a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
index b4c2bb1d223c9..06b89adc597f0 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
@@ -55,9 +55,10 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: move.b %d0, %d3
; ATOMIC-NEXT: sub.b %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.b %d0, %d2
-; ATOMIC-NEXT: bne .LBB0_1
+; ATOMIC-NEXT: beq .LBB0_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -81,9 +82,10 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.b %d0, %d3
; ATOMIC-PIC-NEXT: sub.b %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.b %d0, %d2
-; ATOMIC-PIC-NEXT: bne .LBB0_1
+; ATOMIC-PIC-NEXT: beq .LBB0_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #8, %sp
@@ -137,9 +139,10 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: move.w %d0, %d3
; ATOMIC-NEXT: sub.w %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.w %d0, %d2
-; ATOMIC-NEXT: bne .LBB1_1
+; ATOMIC-NEXT: beq .LBB1_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -163,9 +166,10 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.w %d0, %d3
; ATOMIC-PIC-NEXT: sub.w %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.w %d0, %d2
-; ATOMIC-PIC-NEXT: bne .LBB1_1
+; ATOMIC-PIC-NEXT: beq .LBB1_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #8, %sp
@@ -215,9 +219,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: move.l %d0, %d3
; ATOMIC-NEXT: sub.l %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.l %d0, %d2
-; ATOMIC-NEXT: bne .LBB2_1
+; ATOMIC-NEXT: beq .LBB2_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -241,9 +246,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.l %d0, %d3
; ATOMIC-PIC-NEXT: sub.l %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.l %d0, %d2
-; ATOMIC-PIC-NEXT: bne .LBB2_1
+; ATOMIC-PIC-NEXT: beq .LBB2_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #8, %sp
@@ -353,9 +359,10 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: move.b %d0, %d3
; ATOMIC-NEXT: sub.b %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.b %d0, %d2
-; ATOMIC-NEXT: bne .LBB4_1
+; ATOMIC-NEXT: beq .LBB4_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -379,9 +386,10 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.b %d0, %d3
; ATOMIC-PIC-NEXT: sub.b %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.b %d0, %d2
-; ATOMIC-PIC-NEXT: bne .LBB4_1
+; ATOMIC-PIC-NEXT: beq .LBB4_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #8, %sp
@@ -444,9 +452,10 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: move.w %d1, %d3
; ATOMIC-NEXT: sub.w %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.w %d1, %d2
-; ATOMIC-NEXT: bne .LBB5_1
+; ATOMIC-NEXT: beq .LBB5_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -471,9 +480,10 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.w %d1, %d3
; ATOMIC-PIC-NEXT: sub.w %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.w %d1, %d2
-; ATOMIC-PIC-NEXT: bne .LBB5_1
+; ATOMIC-PIC-NEXT: beq .LBB5_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #8, %sp
@@ -522,9 +532,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: move.l %d0, %d3
; ATOMIC-NEXT: sub.l %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.l %d0, %d2
-; ATOMIC-NEXT: beq .LBB6_4
+; ATOMIC-NEXT: bne .LBB6_4
; ATOMIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d2, %d0
@@ -557,9 +568,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.l %d0, %d3
; ATOMIC-PIC-NEXT: sub.l %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.l %d0, %d2
-; ATOMIC-PIC-NEXT: beq .LBB6_4
+; ATOMIC-PIC-NEXT: bne .LBB6_4
; ATOMIC-PIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.l %d2, %d0
@@ -818,9 +830,10 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: move.b %d0, %d3
; ATOMIC-NEXT: sub.b %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.b %d0, %d2
-; ATOMIC-NEXT: beq .LBB8_4
+; ATOMIC-NEXT: bne .LBB8_4
; ATOMIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.b %d2, %d0
@@ -853,9 +866,10 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.b %d0, %d3
; ATOMIC-PIC-NEXT: sub.b %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.b %d0, %d2
-; ATOMIC-PIC-NEXT: beq .LBB8_4
+; ATOMIC-PIC-NEXT: bne .LBB8_4
; ATOMIC-PIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.b %d2, %d0
@@ -918,9 +932,10 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: move.w %d0, %d3
; ATOMIC-NEXT: sub.w %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.w %d0, %d2
-; ATOMIC-NEXT: beq .LBB9_4
+; ATOMIC-NEXT: bne .LBB9_4
; ATOMIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.w %d2, %d0
@@ -953,9 +968,10 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.w %d0, %d3
; ATOMIC-PIC-NEXT: sub.w %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.w %d0, %d2
-; ATOMIC-PIC-NEXT: beq .LBB9_4
+; ATOMIC-PIC-NEXT: bne .LBB9_4
; ATOMIC-PIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.w %d2, %d0
@@ -1017,9 +1033,10 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: move.w %d0, %d3
; ATOMIC-NEXT: sub.w %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.w %d0, %d2
-; ATOMIC-NEXT: bne .LBB10_1
+; ATOMIC-NEXT: beq .LBB10_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -1041,9 +1058,10 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.w %d0, %d3
; ATOMIC-PIC-NEXT: sub.w %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.w %d0, %d2
-; ATOMIC-PIC-NEXT: bne .LBB10_1
+; ATOMIC-PIC-NEXT: beq .LBB10_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #8, %sp
@@ -1092,9 +1110,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: move.l %d0, %d3
; ATOMIC-NEXT: sub.l %d2, %d3
; ATOMIC-NEXT: seq %d2
-; ATOMIC-NEXT: sub.b #1, %d2
+; ATOMIC-NEXT: and.b #1, %d2
+; ATOMIC-NEXT: cmpi.b #0, %d2
; ATOMIC-NEXT: move.l %d0, %d2
-; ATOMIC-NEXT: bne .LBB11_1
+; ATOMIC-NEXT: beq .LBB11_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-NEXT: adda.l #8, %sp
@@ -1116,9 +1135,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.l %d0, %d3
; ATOMIC-PIC-NEXT: sub.l %d2, %d3
; ATOMIC-PIC-NEXT: seq %d2
-; ATOMIC-PIC-NEXT: sub.b #1, %d2
+; ATOMIC-PIC-NEXT: and.b #1, %d2
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
; ATOMIC-PIC-NEXT: move.l %d0, %d2
-; ATOMIC-PIC-NEXT: bne .LBB11_1
+; ATOMIC-PIC-NEXT: beq .LBB11_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #8, %sp
@@ -1175,9 +1195,10 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-NEXT: move.b %d0, %d2
; ATOMIC-NEXT: sub.b %d1, %d2
; ATOMIC-NEXT: seq %d1
-; ATOMIC-NEXT: sub.b #1, %d1
+; ATOMIC-NEXT: and.b #1, %d1
+; ATOMIC-NEXT: cmpi.b #0, %d1
; ATOMIC-NEXT: move.b %d0, %d1
-; ATOMIC-NEXT: bne .LBB12_1
+; ATOMIC-NEXT: beq .LBB12_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
@@ -1201,9 +1222,10 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: move.b %d0, %d2
; ATOMIC-PIC-NEXT: sub.b %d1, %d2
; ATOMIC-PIC-NEXT: seq %d1
-; ATOMIC-PIC-NEXT: sub.b #1, %d1
+; ATOMIC-PIC-NEXT: and.b #1, %d1
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
; ATOMIC-PIC-NEXT: move.b %d0, %d1
-; ATOMIC-PIC-NEXT: bne .LBB12_1
+; ATOMIC-PIC-NEXT: beq .LBB12_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #4, %sp
@@ -1262,9 +1284,10 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-NEXT: move.w %d0, %d2
; ATOMIC-NEXT: sub.w %d1, %d2
; ATOMIC-NEXT: seq %d1
-; ATOMIC-NEXT: sub.b #1, %d1
+; ATOMIC-NEXT: and.b #1, %d1
+; ATOMIC-NEXT: cmpi.b #0, %d1
; ATOMIC-NEXT: move.w %d0, %d1
-; ATOMIC-NEXT: bne .LBB13_1
+; ATOMIC-NEXT: beq .LBB13_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
@@ -1288,9 +1311,10 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: move.w %d0, %d2
; ATOMIC-PIC-NEXT: sub.w %d1, %d2
; ATOMIC-PIC-NEXT: seq %d1
-; ATOMIC-PIC-NEXT: sub.b #1, %d1
+; ATOMIC-PIC-NEXT: and.b #1, %d1
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
; ATOMIC-PIC-NEXT: move.w %d0, %d1
-; ATOMIC-PIC-NEXT: bne .LBB13_1
+; ATOMIC-PIC-NEXT: beq .LBB13_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #4, %sp
@@ -1349,9 +1373,10 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-NEXT: move.l %d0, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
; ATOMIC-NEXT: seq %d1
-; ATOMIC-NEXT: sub.b #1, %d1
+; ATOMIC-NEXT: and.b #1, %d1
+; ATOMIC-NEXT: cmpi.b #0, %d1
; ATOMIC-NEXT: move.l %d0, %d1
-; ATOMIC-NEXT: bne .LBB14_1
+; ATOMIC-NEXT: beq .LBB14_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-NEXT: adda.l #4, %sp
@@ -1375,9 +1400,10 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: move.l %d0, %d2
; ATOMIC-PIC-NEXT: sub.l %d1, %d2
; ATOMIC-PIC-NEXT: seq %d1
-; ATOMIC-PIC-NEXT: sub.b #1, %d1
+; ATOMIC-PIC-NEXT: and.b #1, %d1
+; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
; ATOMIC-PIC-NEXT: move.l %d0, %d1
-; ATOMIC-PIC-NEXT: bne .LBB14_1
+; ATOMIC-PIC-NEXT: beq .LBB14_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; ATOMIC-PIC-NEXT: adda.l #4, %sp
diff --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll
index d3a8bbb0b0c8f..01dfaeb1b2ec2 100644
--- a/llvm/test/CodeGen/M68k/Control/cmp.ll
+++ b/llvm/test/CodeGen/M68k/Control/cmp.ll
@@ -84,6 +84,7 @@ define i64 @test3(i64 %x) nounwind {
; CHECK-NEXT: seq %d0
; CHECK-NEXT: move.l %d0, %d1
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
%t = icmp eq i64 %x, 0
@@ -103,6 +104,7 @@ define i64 @test4(i64 %x) nounwind {
; CHECK-NEXT: subx.l %d0, %d1
; CHECK-NEXT: slt %d1
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
@@ -144,6 +146,7 @@ define i32 @test7(i64 %res) nounwind {
; CHECK-NEXT: cmpi.l #0, (4,%sp)
; CHECK-NEXT: seq %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: rts
entry:
%lnot = icmp ult i64 %res, 4294967296
@@ -158,6 +161,7 @@ define i32 @test8(i64 %res) nounwind {
; CHECK-NEXT: sub.l #3, %d0
; CHECK-NEXT: scs %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: rts
entry:
%lnot = icmp ult i64 %res, 12884901888
@@ -173,6 +177,7 @@ define i32 @test11(i64 %l) nounwind {
; CHECK-NEXT: sub.l #32768, %d0
; CHECK-NEXT: seq %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: rts
entry:
%shr.mask = and i64 %l, -140737488355328
@@ -240,6 +245,7 @@ define zeroext i1 @test15(i32 %bf.load, i32 %n) {
; CHECK-NEXT: or.b %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: rts
%bf.lshr = lshr i32 %bf.load, 16
%cmp2 = icmp eq i32 %bf.lshr, 0
@@ -288,20 +294,24 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
; CHECK-NEXT: ; %bb.0:
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -8
-; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
+; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: move.l #16777215, %d0
; CHECK-NEXT: and.l (8,%sp), %d0
; CHECK-NEXT: sne %d1
; CHECK-NEXT: and.l #255, %d1
-; CHECK-NEXT: move.l (16,%sp), %a0
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: move.b (15,%sp), %d2
; CHECK-NEXT: and.l #255, %d2
; CHECK-NEXT: add.l %d1, %d2
-; CHECK-NEXT: sne (%a0)
+; CHECK-NEXT: sne %d1
+; CHECK-NEXT: and.b #1, %d1
+; CHECK-NEXT: move.l (16,%sp), %a0
+; CHECK-NEXT: move.b %d1, (%a0)
; CHECK-NEXT: cmpi.l #0, %d0
-; CHECK-NEXT: lea (d,%pc), %a0
-; CHECK-NEXT: sne (%a0)
-; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
+; CHECK-NEXT: sne %d0
+; CHECK-NEXT: and.b #1, %d0
+; CHECK-NEXT: move.b %d0, (d,%pc)
+; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
%bf.shl = shl i32 %bf.load, 8
diff --git a/llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll b/llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
index 90d2be017ecdb..9c9033e02f48e 100644
--- a/llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
+++ b/llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
@@ -16,6 +16,7 @@ define internal void @select_i32(i32 %self, ptr nonnull %value) {
; CHECK-NEXT: bne .LBB0_2
; CHECK-NEXT: ; %bb.1: ; %start
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: cmpi.l #0, %d1
; CHECK-NEXT: bne .LBB0_3
; CHECK-NEXT: .LBB0_2: ; %null
@@ -60,6 +61,7 @@ define internal void @select_i16(i16 %self, ptr nonnull %value) {
; CHECK-NEXT: bne .LBB1_2
; CHECK-NEXT: ; %bb.1: ; %start
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.w #1, %d1
; CHECK-NEXT: cmpi.w #0, %d1
; CHECK-NEXT: bne .LBB1_3
; CHECK-NEXT: .LBB1_2: ; %null
@@ -93,18 +95,26 @@ define internal void @select_i8(i8 %self, ptr nonnull %value) {
; CHECK-LABEL: select_i8:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; %start
-; CHECK-NEXT: move.l (8,%sp), %d0
-; CHECK-NEXT: cmpi.b #0, (7,%sp)
-; CHECK-NEXT: sne %d1
-; CHECK-NEXT: bne .LBB2_2
-; CHECK-NEXT: ; %bb.1: ; %start
-; CHECK-NEXT: cmpi.b #0, %d1
-; CHECK-NEXT: bne .LBB2_3
-; CHECK-NEXT: .LBB2_2: ; %null
-; CHECK-NEXT: suba.l %a0, %a0
-; CHECK-NEXT: move.l %d0, (%a0)
-; CHECK-NEXT: .LBB2_3: ; %exit
-; CHECK-NEXT: rts
+; CHECK-NEXT: suba.l #4, %sp
+; CHECK-NEXT: .cfi_def_cfa_offset -8
+; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
+; CHECK-NEXT: cmpi.b #0, (11,%sp)
+; CHECK-NEXT: move.w %ccr, %d2
+; CHECK-NEXT: sne %d1
+; CHECK-NEXT: move.l (12,%sp), %d0
+; CHECK-NEXT: move.w %d2, %ccr
+; CHECK-NEXT: bne .LBB2_2
+; CHECK-NEXT: ; %bb.1: ; %start
+; CHECK-NEXT: and.b #1, %d1
+; CHECK-NEXT: cmpi.b #0, %d1
+; CHECK-NEXT: bne .LBB2_3
+; CHECK-NEXT: .LBB2_2: ; %null
+; CHECK-NEXT: suba.l %a0, %a0
+; CHECK-NEXT: move.l %d0, (%a0)
+; CHECK-NEXT: .LBB2_3: ; %exit
+; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
+; CHECK-NEXT: adda.l #4, %sp
+; CHECK-NEXT: rts
start:
%2 = icmp eq i8 %self, 0
%3 = select i1 %2, i8 0, i8 1
diff --git a/llvm/test/CodeGen/M68k/Control/setcc.ll b/llvm/test/CodeGen/M68k/Control/setcc.ll
index 9e03f9b90842a..a2c24c94ca4cc 100644
--- a/llvm/test/CodeGen/M68k/Control/setcc.ll
+++ b/llvm/test/CodeGen/M68k/Control/setcc.ll
@@ -11,6 +11,7 @@ define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
; CHECK-NEXT: sub.l #26, %d0
; CHECK-NEXT: shi %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: lsl.l #5, %d0
; CHECK-NEXT: rts
entry:
@@ -27,6 +28,7 @@ define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
; CHECK-NEXT: sub.l #26, %d0
; CHECK-NEXT: scs %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: lsl.l #5, %d0
; CHECK-NEXT: rts
entry:
@@ -39,16 +41,17 @@ define fastcc i64 @t3(i64 %x) nounwind readnone ssp {
; CHECK-LABEL: t3:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: suba.l #4, %sp
-; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
+; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: moveq #0, %d2
; CHECK-NEXT: sub.l #18, %d1
; CHECK-NEXT: subx.l %d2, %d0
; CHECK-NEXT: scs %d0
; CHECK-NEXT: move.l %d0, %d1
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: lsl.l #6, %d1
; CHECK-NEXT: move.l %d2, %d0
-; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
+; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
entry:
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