[llvm] d455d45 - [RISCV][VLOPT] Added support for several vector crypto instructions (#153071)
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Tue Aug 12 08:05:07 PDT 2025
Author: Mikhail R. Gadelha
Date: 2025-08-12T12:05:03-03:00
New Revision: d455d45654e8c0ffc53e3965316e411db595c4a9
URL: https://github.com/llvm/llvm-project/commit/d455d45654e8c0ffc53e3965316e411db595c4a9
DIFF: https://github.com/llvm/llvm-project/commit/d455d45654e8c0ffc53e3965316e411db595c4a9.diff
LOG: [RISCV][VLOPT] Added support for several vector crypto instructions (#153071)
This PR adds support for the following instructions to the RISC-V
VLOptimizer: vandn.vx, vandn.vv, vbrev.v, vclz.v, vcpop.v, vctz.v,
vror.vi, vror.vx, vror.vv, vrol.vx, vrol.vv.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 37a71e8ec7689..28c8f401321fd 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -491,8 +491,31 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
// vfirst find-first-set mask bit
case RISCV::VCPOP_M:
case RISCV::VFIRST_M:
+ // Vector Bit-manipulation Instructions (Zvbb)
+ // Vector And-Not
+ case RISCV::VANDN_VV:
+ case RISCV::VANDN_VX:
+ // Vector Reverse Bits in Elements
+ case RISCV::VBREV_V:
+ // Vector Count Leading Zeros
+ case RISCV::VCLZ_V:
+ // Vector Count Trailing Zeros
+ case RISCV::VCTZ_V:
+ // Vector Population Count
+ case RISCV::VCPOP_V:
+ // Vector Rotate Left
+ case RISCV::VROL_VV:
+ case RISCV::VROL_VX:
+ // Vector Rotate Right
+ case RISCV::VROR_VI:
+ case RISCV::VROR_VV:
+ case RISCV::VROR_VX:
return MILog2SEW;
+ // Vector Widening Shift Left Logical (Zvbb)
+ case RISCV::VWSLL_VI:
+ case RISCV::VWSLL_VX:
+ case RISCV::VWSLL_VV:
// Vector Widening Integer Add/Subtract
// Def uses EEW=2*SEW . Operands use EEW=SEW.
case RISCV::VWADDU_VV:
@@ -503,9 +526,6 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
case RISCV::VWADD_VX:
case RISCV::VWSUB_VV:
case RISCV::VWSUB_VX:
- case RISCV::VWSLL_VI:
- case RISCV::VWSLL_VX:
- case RISCV::VWSLL_VV:
// Vector Widening Integer Multiply Instructions
// Destination EEW=2*SEW. Source EEW=SEW.
case RISCV::VWMUL_VV:
@@ -1020,12 +1040,29 @@ static bool isSupportedInstr(const MachineInstr &MI) {
case RISCV::VNCLIP_WV:
case RISCV::VNCLIP_WX:
case RISCV::VNCLIP_WI:
-
- // Vector Crypto
+ // Vector Bit-manipulation Instructions (Zvbb)
+ // Vector And-Not
+ case RISCV::VANDN_VV:
+ case RISCV::VANDN_VX:
+ // Vector Reverse Bits in Elements
+ case RISCV::VBREV_V:
+ // Vector Count Leading Zeros
+ case RISCV::VCLZ_V:
+ // Vector Count Trailing Zeros
+ case RISCV::VCTZ_V:
+ // Vector Population Count
+ case RISCV::VCPOP_V:
+ // Vector Rotate Left
+ case RISCV::VROL_VV:
+ case RISCV::VROL_VX:
+ // Vector Rotate Right
+ case RISCV::VROR_VI:
+ case RISCV::VROR_VV:
+ case RISCV::VROR_VX:
+ // Vector Widening Shift Left Logical
case RISCV::VWSLL_VI:
case RISCV::VWSLL_VX:
case RISCV::VWSLL_VV:
-
// Vector Mask Instructions
// Vector Mask-Register Logical Instructions
// vmsbf.m set-before-first mask bit
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
index 65d3e3f8f0d3b..38652b2539996 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
@@ -3402,9 +3402,8 @@ define <vscale x 4 x double> @vfrec7(<vscale x 4 x float> %a) {
define <vscale x 4 x i32> @vandn_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
; CHECK-LABEL: vandn_vv:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vandn.vv v10, v8, v10
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vandn.vv v10, v8, v10
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vandn.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
@@ -3415,9 +3414,8 @@ define <vscale x 4 x i32> @vandn_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b
define <vscale x 4 x i32> @vandn_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
; CHECK-LABEL: vandn_vx:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
-; CHECK-NEXT: vandn.vx v10, v8, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vandn.vx v10, v8, a0
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vandn.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
@@ -3428,9 +3426,8 @@ define <vscale x 4 x i32> @vandn_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
define <vscale x 4 x i32> @vbrev_v(<vscale x 4 x i32> %a, iXLen %vl) {
; CHECK-LABEL: vbrev_v:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vbrev.v v10, v8
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vbrev.v v10, v8
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vbrev.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
@@ -3441,9 +3438,8 @@ define <vscale x 4 x i32> @vbrev_v(<vscale x 4 x i32> %a, iXLen %vl) {
define <vscale x 4 x i32> @vclz_v(<vscale x 4 x i32> %a, iXLen %vl) {
; CHECK-LABEL: vclz_v:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vclz.v v10, v8
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vclz.v v10, v8
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vclz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
@@ -3454,9 +3450,8 @@ define <vscale x 4 x i32> @vclz_v(<vscale x 4 x i32> %a, iXLen %vl) {
define <vscale x 4 x i32> @vcpop_v(<vscale x 4 x i32> %a, iXLen %vl) {
; CHECK-LABEL: vcpop_v:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vcpop.v v10, v8
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vcpop.v v10, v8
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vcpopv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
@@ -3467,9 +3462,8 @@ define <vscale x 4 x i32> @vcpop_v(<vscale x 4 x i32> %a, iXLen %vl) {
define <vscale x 4 x i32> @vctz_v(<vscale x 4 x i32> %a, iXLen %vl) {
; CHECK-LABEL: vctz_v:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vctz.v v10, v8
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vctz.v v10, v8
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vctz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
@@ -3480,9 +3474,8 @@ define <vscale x 4 x i32> @vctz_v(<vscale x 4 x i32> %a, iXLen %vl) {
define <vscale x 4 x i32> @vror_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
; CHECK-LABEL: vror_vv:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vror.vv v10, v8, v10
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vror.vv v10, v8, v10
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
@@ -3493,9 +3486,8 @@ define <vscale x 4 x i32> @vror_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b,
define <vscale x 4 x i32> @vror_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
; CHECK-LABEL: vror_vx:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
-; CHECK-NEXT: vror.vx v10, v8, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vror.vx v10, v8, a0
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)
@@ -3506,9 +3498,8 @@ define <vscale x 4 x i32> @vror_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
define <vscale x 4 x i32> @vror_vi(<vscale x 4 x i32> %a, iXLen %vl) {
; CHECK-LABEL: vror_vi:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vror.vi v10, v8, 5
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vror.vi v10, v8, 5
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)
@@ -3519,9 +3510,8 @@ define <vscale x 4 x i32> @vror_vi(<vscale x 4 x i32> %a, iXLen %vl) {
define <vscale x 4 x i32> @vrol_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
; CHECK-LABEL: vrol_vv:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vrol.vv v10, v8, v10
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vrol.vv v10, v8, v10
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vrol.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
@@ -3532,9 +3522,8 @@ define <vscale x 4 x i32> @vrol_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b,
define <vscale x 4 x i32> @vrol_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
; CHECK-LABEL: vrol_vx:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
-; CHECK-NEXT: vrol.vx v10, v8, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vrol.vx v10, v8, a0
; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vrol.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)
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