[llvm] 5d099c2 - [AArch64][GlobalISel] Add 128bit insert and extract vector test coverage. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 12 05:50:41 PDT 2025
Author: David Green
Date: 2025-08-12T13:50:36+01:00
New Revision: 5d099c2831f83bb8b8b2ae6621ef49282bc7283d
URL: https://github.com/llvm/llvm-project/commit/5d099c2831f83bb8b8b2ae6621ef49282bc7283d
DIFF: https://github.com/llvm/llvm-project/commit/5d099c2831f83bb8b8b2ae6621ef49282bc7283d.diff
LOG: [AArch64][GlobalISel] Add 128bit insert and extract vector test coverage. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/insertextract.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll
index 5c89316e5f570..13a43d6d35239 100644
--- a/llvm/test/CodeGen/AArch64/insertextract.ll
+++ b/llvm/test/CodeGen/AArch64/insertextract.ll
@@ -1,6 +1,17 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for insert_v2i128_0
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2i128_1
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2i128_c
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2fp128_0
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2fp128_1
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2fp128_c
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v2i128_0
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v2i128_1
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v2i128_c
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v2fp128_c
define <2 x double> @insert_v2f64_0(<2 x double> %a, double %b, i32 %c) {
; CHECK-LABEL: insert_v2f64_0:
@@ -1312,6 +1323,137 @@ entry:
ret <4 x i64> %d
}
+define <2 x i128> @insert_v2i128_0(<2 x i128> %a, i128 %b, i32 %c) {
+; CHECK-LABEL: insert_v2i128_0:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adds x2, x2, x2
+; CHECK-NEXT: mov x1, x5
+; CHECK-NEXT: mov x0, x4
+; CHECK-NEXT: adc x3, x3, x3
+; CHECK-NEXT: ret
+entry:
+ %aa = add <2 x i128> %a, %a
+ %d = insertelement <2 x i128> %aa, i128 %b, i32 0
+ ret <2 x i128> %d
+}
+
+define <2 x i128> @insert_v2i128_1(<2 x i128> %a, i128 %b, i32 %c) {
+; CHECK-LABEL: insert_v2i128_1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adds x0, x0, x0
+; CHECK-NEXT: mov x3, x5
+; CHECK-NEXT: mov x2, x4
+; CHECK-NEXT: adc x1, x1, x1
+; CHECK-NEXT: ret
+entry:
+ %aa = add <2 x i128> %a, %a
+ %d = insertelement <2 x i128> %aa, i128 %b, i32 1
+ ret <2 x i128> %d
+}
+
+define <2 x i128> @insert_v2i128_c(<2 x i128> %a, i128 %b, i32 %c) {
+; CHECK-LABEL: insert_v2i128_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: // kill: def $w6 killed $w6 def $x6
+; CHECK-NEXT: adds x8, x0, x0
+; CHECK-NEXT: and x11, x6, #0x1
+; CHECK-NEXT: mov x12, sp
+; CHECK-NEXT: adc x9, x1, x1
+; CHECK-NEXT: adds x10, x2, x2
+; CHECK-NEXT: add x11, x12, x11, lsl #4
+; CHECK-NEXT: str x8, [sp]
+; CHECK-NEXT: adc x8, x3, x3
+; CHECK-NEXT: str x10, [sp, #16]
+; CHECK-NEXT: str x4, [x11]
+; CHECK-NEXT: str x8, [sp, #24]
+; CHECK-NEXT: str x9, [sp, #8]
+; CHECK-NEXT: str x5, [x11, #8]
+; CHECK-NEXT: ldp x0, x1, [sp]
+; CHECK-NEXT: ldp x2, x3, [sp, #16]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
+entry:
+ %aa = add <2 x i128> %a, %a
+ %d = insertelement <2 x i128> %aa, i128 %b, i32 %c
+ ret <2 x i128> %d
+}
+
+define <2 x fp128> @insert_v2fp128_0(<2 x fp128> %a, fp128 %b, i32 %c) {
+; CHECK-LABEL: insert_v2fp128_0:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: str q2, [sp] // 16-byte Folded Spill
+; CHECK-NEXT: bl __addtf3
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
+entry:
+ %aa = fadd <2 x fp128> %a, %a
+ %d = insertelement <2 x fp128> %aa, fp128 %b, i32 0
+ ret <2 x fp128> %d
+}
+
+define <2 x fp128> @insert_v2fp128_1(<2 x fp128> %a, fp128 %b, i32 %c) {
+; CHECK-LABEL: insert_v2fp128_1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: str q2, [sp] // 16-byte Folded Spill
+; CHECK-NEXT: bl __addtf3
+; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
+entry:
+ %aa = fadd <2 x fp128> %a, %a
+ %d = insertelement <2 x fp128> %aa, fp128 %b, i32 1
+ ret <2 x fp128> %d
+}
+
+define <2 x fp128> @insert_v2fp128_c(<2 x fp128> %a, fp128 %b, i32 %c) {
+; CHECK-LABEL: insert_v2fp128_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #96
+; CHECK-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 96
+; CHECK-NEXT: .cfi_offset w19, -8
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: mov w19, w0
+; CHECK-NEXT: str q2, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: bl __addtf3
+; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: bl __addtf3
+; CHECK-NEXT: str q0, [sp, #64]
+; CHECK-NEXT: ldp q3, q0, [sp, #16] // 32-byte Folded Reload
+; CHECK-NEXT: and x8, x19, #0x1
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp, #48]
+; CHECK-NEXT: str q0, [x9, x8, lsl #4]
+; CHECK-NEXT: ldp q0, q1, [sp, #48]
+; CHECK-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #96
+; CHECK-NEXT: ret
+entry:
+ %aa = fadd <2 x fp128> %a, %a
+ %d = insertelement <2 x fp128> %aa, fp128 %b, i32 %c
+ ret <2 x fp128> %d
+}
+
define double @extract_v2f64_0(<2 x double> %a, i32 %c) {
; CHECK-LABEL: extract_v2f64_0:
; CHECK: // %bb.0: // %entry
@@ -2573,3 +2715,94 @@ entry:
%d = extractelement <4 x i64> %a, i32 %c
ret i64 %d
}
+
+define i128 @extract_v2i128_0(<2 x i128> %a, i32 %c) {
+; CHECK-LABEL: extract_v2i128_0:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adds x0, x0, x0
+; CHECK-NEXT: adc x1, x1, x1
+; CHECK-NEXT: ret
+entry:
+ %b = add <2 x i128> %a, %a
+ %d = extractelement <2 x i128> %b, i32 0
+ ret i128 %d
+}
+
+define i128 @extract_v2i128_1(<2 x i128> %a, i32 %c) {
+; CHECK-LABEL: extract_v2i128_1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adds x0, x2, x2
+; CHECK-NEXT: adc x1, x3, x3
+; CHECK-NEXT: ret
+entry:
+ %b = add <2 x i128> %a, %a
+ %d = extractelement <2 x i128> %b, i32 1
+ ret i128 %d
+}
+
+define i128 @extract_v2i128_c(<2 x i128> %a, i32 %c) {
+; CHECK-LABEL: extract_v2i128_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #64
+; CHECK-NEXT: .cfi_def_cfa_offset 64
+; CHECK-NEXT: adds x9, x0, x0
+; CHECK-NEXT: mov w8, w4
+; CHECK-NEXT: adc x10, x1, x1
+; CHECK-NEXT: adds x11, x2, x2
+; CHECK-NEXT: fmov d1, x9
+; CHECK-NEXT: fmov d0, x11
+; CHECK-NEXT: adc x12, x3, x3
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: and x9, x8, #0x3
+; CHECK-NEXT: add w8, w8, #1
+; CHECK-NEXT: mov x11, sp
+; CHECK-NEXT: mov v1.d[1], x10
+; CHECK-NEXT: add x10, sp, #32
+; CHECK-NEXT: and x8, x8, #0x3
+; CHECK-NEXT: mov v0.d[1], x12
+; CHECK-NEXT: stp q1, q0, [sp]
+; CHECK-NEXT: stp q1, q0, [sp, #32]
+; CHECK-NEXT: ldr x0, [x10, x9, lsl #3]
+; CHECK-NEXT: ldr x1, [x11, x8, lsl #3]
+; CHECK-NEXT: add sp, sp, #64
+; CHECK-NEXT: ret
+entry:
+ %b = add <2 x i128> %a, %a
+ %d = extractelement <2 x i128> %b, i32 %c
+ ret i128 %d
+}
+
+define fp128 @extract_v2fp128_0(<2 x fp128> %a, i32 %c) {
+; CHECK-LABEL: extract_v2fp128_0:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ret
+entry:
+ %d = extractelement <2 x fp128> %a, i32 0
+ ret fp128 %d
+}
+
+define fp128 @extract_v2fp128_1(<2 x fp128> %a, i32 %c) {
+; CHECK-LABEL: extract_v2fp128_1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
+entry:
+ %d = extractelement <2 x fp128> %a, i32 1
+ ret fp128 %d
+}
+
+define fp128 @extract_v2fp128_c(<2 x fp128> %a, i32 %c) {
+; CHECK-LABEL: extract_v2fp128_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp q0, q1, [sp, #-32]!
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: and x8, x0, #0x1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: ldr q0, [x9, x8, lsl #4]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
+entry:
+ %d = extractelement <2 x fp128> %a, i32 %c
+ ret fp128 %d
+}
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