[llvm] 296e057 - [DAG] SelectionDAG::canCreateUndefOrPoison - add ISD::FMA/FMAD + tests (#152187)

[via llvm-commits]

Author: Seraphimt
Date: 2025-08-12T17:17:46+09:00
New Revision: 296e057d0bf29cb6ac30ce1aecd27c86017c4744

URL: https://github.com/llvm/llvm-project/commit/296e057d0bf29cb6ac30ce1aecd27c86017c4744
DIFF: https://github.com/llvm/llvm-project/commit/296e057d0bf29cb6ac30ce1aecd27c86017c4744.diff

LOG: [DAG] SelectionDAG::canCreateUndefOrPoison - add ISD::FMA/FMAD + tests (#152187)

In SelectionDAG::canCreateUndefOrPoison add case ISD::FMA/FMAD + tests.
Fixing #147693

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>

Added: 
    llvm/test/CodeGen/AArch64/fma-fneg-combine.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 5ef1746333040..68ea72c732e1e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5628,6 +5628,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   case ISD::FDIV:
   case ISD::FREM:
   case ISD::FCOPYSIGN:
+  case ISD::FMA:
+  case ISD::FMAD:
   case ISD::FP_EXTEND:
     // No poison except from flags (which is handled above)
     return false;

diff  --git a/llvm/test/CodeGen/AArch64/fma-fneg-combine.ll b/llvm/test/CodeGen/AArch64/fma-fneg-combine.ll
new file mode 100644
index 0000000000000..936cc6a7d366f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fma-fneg-combine.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK
+
+define float @positive_case_fma(float %a0, float %a1, float %a2) {
+; CHECK-LABEL: positive_case_fma:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fnmadd s0, s0, s1, s2
+; CHECK-NEXT:    ret
+  %fma = call float @llvm.fma.f32(float %a0, float %a1, float %a2)
+  %freeze = freeze float %fma
+  %fneg = fneg float %freeze
+  ret float %fneg
+}
+
+define float @negative_case_fma(float %a0, float %a1) {
+; CHECK-LABEL: negative_case_fma:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fnmadd s0, s0, s1, s0
+; CHECK-NEXT:    ret
+  %fma = call float @llvm.fma.f32(float %a0, float %a1, float poison)
+  %freeze = freeze float %fma
+  %fneg = fneg float %freeze
+  ret float %fneg
+}
+
+define float @positive_case_fmad(float %a0, float %a1, float %a2) {
+; CHECK-LABEL: positive_case_fmad:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fnmadd s0, s0, s1, s2
+; CHECK-NEXT:    ret
+  %fma = call float @llvm.fma.f32(float %a0, float %a1, float %a2)
+  %freeze = freeze float %fma
+  %fneg = fneg float %freeze
+  ret float %fneg
+}
+
+define float @negative_case_fmad(float %a0, float %a1) {
+; CHECK-LABEL: negative_case_fmad:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fnmadd s0, s0, s1, s0
+; CHECK-NEXT:    ret
+  %fmad = call float @llvm.fmuladd.f32(float %a0, float %a1, float poison)
+  %freeze = freeze float %fmad
+  %fneg = fneg float %freeze
+  ret float %fneg
+}
+