[llvm] [AMDGPU] Legalize 64bit elements for BUILD_VECTOR on gfx942 (PR #145052)

[Chris Jackson via llvm-commits]

================
@@ -16017,6 +16057,93 @@ SDValue SITargetLowering::performSelectCombine(SDNode *N,
                          SelectLHS, SelectRHS);
 }
 
+SDValue
+SITargetLowering::performBuildVectorCombine(SDNode *N,
+                                            DAGCombinerInfo &DCI) const {
+  // TODO: legalize for all targets instead of just v_mov_b64 enabled ones.
+  const GCNSubtarget *ST = getSubtarget();
+  if (DCI.Level < AfterLegalizeDAG || !ST->hasMovB64())
+    return SDValue();
+
+  SelectionDAG &DAG = DCI.DAG;
+  SDLoc SL(N);
+
+  EVT VT = N->getValueType(0);
+  EVT EltVT = VT.getVectorElementType();
+  unsigned SizeBits = VT.getSizeInBits();
+  unsigned EltSize = EltVT.getSizeInBits();
+
+  // Skip if:
+  //  - Value type isn't multiple of 64 bit (e.g., v3i32), or
+  //  - Element type has already been combined into 64b elements
+  if ((SizeBits % 64) != 0 || EltVT == MVT::i64 || EltVT == MVT::f64)
+    return SDValue();
+
+  // Construct the 64b values.
+  SmallVector<uint64_t, 8> ImmVals;
+  uint64_t ImmVal = 0;
+  uint64_t ImmSize = 0;
+  for (SDValue Opand : N->ops()) {
+    // Build_vector with constants only.
+    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Opand);
+    ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Opand);
+    BuildVectorSDNode *BV =
+        dyn_cast<BuildVectorSDNode>(peekThroughBitcasts(Opand));
+
+    if (!C && !FPC && !BV)
+      return SDValue();
+
+    uint64_t Val = 0;
+    if (BV) {
+      if (!BV->isConstant())
+        return SDValue();
+      bool IsLE = DAG.getDataLayout().isLittleEndian();
+      BitVector UndefElements;
+      SmallVector<APInt> RawBits;
+      if (!BV->getConstantRawBits(IsLE, EltSize, RawBits, UndefElements))
+        return SDValue();
+
+      assert(RawBits.size() == 1 &&
+             "BuildVector constant value retrieval expected 1 element");
+
+      if (UndefElements.any())
+        return SDValue();
+
+      Val = RawBits[0].getZExtValue();
+    } else
+      Val = C ? C->getZExtValue()
+              : FPC->getValueAPF().bitcastToAPInt().getZExtValue();
+    ImmVal |= Val << ImmSize;
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chrisjbris wrote:

nit: Might be worth adding a blank line or using braces to help readability for the else case here.

https://github.com/llvm/llvm-project/pull/145052