[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

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@@ -5201,6 +5215,51 @@ SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
 
 static MVT getSVEContainerType(EVT ContentTy);
 
+SDValue
+AArch64TargetLowering::LowerLOOP_DEPENDENCE_MASK(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  uint64_t EltSize = Op.getConstantOperandVal(2);
+  EVT VT = Op.getValueType();
+  // Make sure that the promoted mask size and element size match
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sdesmalen-arm wrote:

I think for this PR, I'd rather see this code falling back on the generic expansion by returning `SDValue()` so that the PR is simpler (even if suboptimal) and functionally correct, and we can get this change to land. Can you split out any improvements to the lowering of these intrinsics to a follow-up PR? Then we'll review that separately.

https://github.com/llvm/llvm-project/pull/117007