[llvm] [IA][RISCV] Recognize deinterleaved loads that could lower to strided segmented loads (PR #151612)

[Mel Chen via llvm-commits]

Mel-Chen wrote:

> Once we had that, I'm tempted to pose the mask recognition as a prior transform to produce a strided.load intrinsic, but I recognize we'd have to produce some illegally typed intermediates. Both options seem a bit ugly, maybe discuss offline?

Yes, in our downstream, the vectorizer generates vp.stride.load + bitcast to represent strided segment accesses, but only when the stride is a runtime stride. When the stride is constant, it can be represented using a wide masked load/store, which corresponds to the currently supported interleaved access with gap mask.

Regarding downstream’s approach for handling runtime stride, it indeed needs to generate a vp.stride.load/store with an element type of segment_size * element_type, and this type is often illegal. We have encountered crashes caused by the InterleavedAccess pass failing to lower such cases into vlsseg. Although this bug has since been fixed, I still feel this approach is somewhat unsafe.

Nevertheless, I think this patch is a good starting point for handling constant strides.

https://github.com/llvm/llvm-project/pull/151612