[llvm] [AArch64] Replace SIMDLongThreeVectorBHSabd with SIMDLongThreeVectorBHS. (PR #152987)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 11 02:55:20 PDT 2025
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/152987
We just need to use a BinOpFrag to share the patterns. This also moves UABDL to where it belongs in with similar instructions, and removes some patterns that are now handled by abd nodes. This is mostly NFC except for GISel, which will catch back up when it handles abd nodes in the same way.
>From 7029dce0153176c2ebe8d6dff7c4b073d84c5e67 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 11 Aug 2025 10:53:57 +0100
Subject: [PATCH] [AArch64] Replace SIMDLongThreeVectorBHSabd with
SIMDLongThreeVectorBHS.
We just need to use a BinOpFrag to share the patterns. This also moves UABDL to
where it belongs in with similar instructions, and removes some patterns that
are now handled by abd nodes. This is mostly NFC except for GISel, which will
catch back up when it handles abd nodes in the same way.
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 38 -------------------
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 26 ++-----------
2 files changed, 4 insertions(+), 60 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index b033f889fbf61..586c4a8dc9c41 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -7400,44 +7400,6 @@ multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
(extract_high_v4i32 (v4i32 V128:$Rm))))]>;
}
-let isCommutable = 1 in
-multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
- SDPatternOperator OpNode = null_frag> {
- def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
- V128, V64, V64,
- asm, ".8h", ".8b", ".8b",
- [(set (v8i16 V128:$Rd),
- (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
- def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
- V128, V128, V128,
- asm#"2", ".8h", ".16b", ".16b",
- [(set (v8i16 V128:$Rd),
- (zext (v8i8 (OpNode (extract_high_v16i8 (v16i8 V128:$Rn)),
- (extract_high_v16i8 (v16i8 V128:$Rm))))))]>;
- def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
- V128, V64, V64,
- asm, ".4s", ".4h", ".4h",
- [(set (v4i32 V128:$Rd),
- (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
- def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
- V128, V128, V128,
- asm#"2", ".4s", ".8h", ".8h",
- [(set (v4i32 V128:$Rd),
- (zext (v4i16 (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
- (extract_high_v8i16 (v8i16 V128:$Rm))))))]>;
- def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
- V128, V64, V64,
- asm, ".2d", ".2s", ".2s",
- [(set (v2i64 V128:$Rd),
- (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
- def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
- V128, V128, V128,
- asm#"2", ".2d", ".4s", ".4s",
- [(set (v2i64 V128:$Rd),
- (zext (v2i32 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
- (extract_high_v4i32 (v4i32 V128:$Rm))))))]>;
-}
-
multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
string asm,
SDPatternOperator OpNode> {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 8cfbff938a395..2f60a8b6fe344 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5707,27 +5707,6 @@ let Predicates = [HasFullFP16] in {
// Advanced SIMD two vector instructions.
//===----------------------------------------------------------------------===//
-defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl", abdu>;
-// Match UABDL in log2-shuffle patterns.
-def : Pat<(abs (v8i16 (sub (zext (v8i8 V64:$opA)),
- (zext (v8i8 V64:$opB))))),
- (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>;
-def : Pat<(abs (v8i16 (sub (zext (extract_high_v16i8 (v16i8 V128:$opA))),
- (zext (extract_high_v16i8 (v16i8 V128:$opB)))))),
- (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>;
-def : Pat<(abs (v4i32 (sub (zext (v4i16 V64:$opA)),
- (zext (v4i16 V64:$opB))))),
- (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>;
-def : Pat<(abs (v4i32 (sub (zext (extract_high_v8i16 (v8i16 V128:$opA))),
- (zext (extract_high_v8i16 (v8i16 V128:$opB)))))),
- (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>;
-def : Pat<(abs (v2i64 (sub (zext (v2i32 V64:$opA)),
- (zext (v2i32 V64:$opB))))),
- (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>;
-def : Pat<(abs (v2i64 (sub (zext (extract_high_v4i32 (v4i32 V128:$opA))),
- (zext (extract_high_v4i32 (v4i32 V128:$opB)))))),
- (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>;
-
defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>;
defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
@@ -6810,7 +6789,8 @@ defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn
let isCommutable = 1 in
defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull", AArch64pmull>;
defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal", abds>;
-defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl", abds>;
+defm SABDL : SIMDLongThreeVectorBHS<0, 0b0111, "sabdl",
+ BinOpFrag<(zext (abds node:$LHS, node:$RHS))>>;
defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
@@ -6830,6 +6810,8 @@ defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal", abdu>;
+defm UABDL : SIMDLongThreeVectorBHS<1, 0b0111, "uabdl",
+ BinOpFrag<(zext (abdu node:$LHS, node:$RHS))>>;
defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
BinOpFrag<(add (zanyext node:$LHS), (zanyext node:$RHS))>>;
defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
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