[llvm] 5bd39a0 - [AArch64][nfc] Remove duplicate [us]addl tests (#152664)
via llvm-commits
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Mon Aug 11 02:21:45 PDT 2025
Author: Cullen Rhodes
Date: 2025-08-11T10:21:41+01:00
New Revision: 5bd39a0060bed29e04db954eff77386473d38bb3
URL: https://github.com/llvm/llvm-project/commit/5bd39a0060bed29e04db954eff77386473d38bb3
DIFF: https://github.com/llvm/llvm-project/commit/5bd39a0060bed29e04db954eff77386473d38bb3.diff
LOG: [AArch64][nfc] Remove duplicate [us]addl tests (#152664)
in the following list we keep the first test:
- extadd[us]_v8i8_i16, test_vaddl_[us]8, [us]addl8h
- extadd[us]_v4i16_i32, test_vaddl_[us]16, [us]addl4s
- extadd[us]_v2i32_i64, test_vaddl_[us]32, [us]addl2d
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
llvm/test/CodeGen/AArch64/arm64-vadd.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-3v
diff .ll b/llvm/test/CodeGen/AArch64/arm64-neon-3v
diff .ll
index 9a1b6a0661e6b..9bafc5b8aea62 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-3v
diff .ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-3v
diff .ll
@@ -34,42 +34,6 @@ declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>)
declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>)
declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>)
-define <8 x i16> @test_vaddl_s8(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: test_vaddl_s8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = sext <8 x i8> %a to <8 x i16>
- %vmovl.i2.i = sext <8 x i8> %b to <8 x i16>
- %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i
- ret <8 x i16> %add.i
-}
-
-define <4 x i32> @test_vaddl_s16(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: test_vaddl_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = sext <4 x i16> %a to <4 x i32>
- %vmovl.i2.i = sext <4 x i16> %b to <4 x i32>
- %add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i
- ret <4 x i32> %add.i
-}
-
-define <2 x i64> @test_vaddl_s32(<2 x i32> %a, <2 x i32> %b) {
-; CHECK-LABEL: test_vaddl_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = sext <2 x i32> %a to <2 x i64>
- %vmovl.i2.i = sext <2 x i32> %b to <2 x i64>
- %add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i
- ret <2 x i64> %add.i
-}
-
define void @test_commutable_vaddl_s8(<8 x i8> %a, <8 x i8> %b, ptr %c) {
; CHECK-LABEL: test_commutable_vaddl_s8:
; CHECK: // %bb.0: // %entry
@@ -87,42 +51,6 @@ entry:
ret void
}
-define <8 x i16> @test_vaddl_u8(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: test_vaddl_u8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = zext <8 x i8> %a to <8 x i16>
- %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>
- %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i
- ret <8 x i16> %add.i
-}
-
-define <4 x i32> @test_vaddl_u16(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: test_vaddl_u16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = zext <4 x i16> %a to <4 x i32>
- %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
- %add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i
- ret <4 x i32> %add.i
-}
-
-define <2 x i64> @test_vaddl_u32(<2 x i32> %a, <2 x i32> %b) {
-; CHECK-LABEL: test_vaddl_u32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = zext <2 x i32> %a to <2 x i64>
- %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
- %add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i
- ret <2 x i64> %add.i
-}
-
define void @test_commutable_vaddl_u8(<8 x i8> %a, <8 x i8> %b, ptr %c) {
; CHECK-LABEL: test_commutable_vaddl_u8:
; CHECK: // %bb.0: // %entry
@@ -2926,9 +2854,9 @@ define <8 x i16> @cmplx_mul_combined_re_im(<8 x i16> noundef %a, i64 %scale.coer
; CHECK-GI-LABEL: cmplx_mul_combined_re_im:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: lsr x9, x0, #16
-; CHECK-GI-NEXT: adrp x8, .LCPI198_0
+; CHECK-GI-NEXT: adrp x8, .LCPI192_0
; CHECK-GI-NEXT: rev32 v4.8h, v0.8h
-; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI198_0]
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI192_0]
; CHECK-GI-NEXT: fmov d1, x9
; CHECK-GI-NEXT: dup v2.8h, v1.h[0]
; CHECK-GI-NEXT: sqneg v1.8h, v2.8h
diff --git a/llvm/test/CodeGen/AArch64/arm64-vadd.ll b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
index d982dbbb1f69b..f9263185f308e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
@@ -170,51 +170,6 @@ declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>) nounwind
declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-define <8 x i16> @saddl8h(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: saddl8h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = load <8 x i8>, ptr %B
- %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @saddl4s(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: saddl4s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
- %tmp1 = load <4 x i16>, ptr %A
- %tmp2 = load <4 x i16>, ptr %B
- %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @saddl2d(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: saddl2d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
- %tmp1 = load <2 x i32>, ptr %A
- %tmp2 = load <2 x i32>, ptr %B
- %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
define <8 x i16> @saddl2_8h(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECK-LABEL: saddl2_8h:
; CHECK: // %bb.0:
@@ -266,52 +221,6 @@ define <2 x i64> @saddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind {
ret <2 x i64> %add.i
}
-define <8 x i16> @uaddl8h(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: uaddl8h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = load <8 x i8>, ptr %B
- %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @uaddl4s(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: uaddl4s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
- %tmp1 = load <4 x i16>, ptr %A
- %tmp2 = load <4 x i16>, ptr %B
- %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @uaddl2d(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: uaddl2d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
- %tmp1 = load <2 x i32>, ptr %A
- %tmp2 = load <2 x i32>, ptr %B
- %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-
define <8 x i16> @uaddl2_8h(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECK-LABEL: uaddl2_8h:
; CHECK: // %bb.0:
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