[llvm] [AArch64] Correct SCVTF instructions for vector input (PR #152974)

[Amina Chabane via llvm-commits]

https://github.com/Amichaxx created https://github.com/llvm/llvm-project/pull/152974

Improve the pattern matching for scalar floating-point conversion instructions on AArch64, ensuring that more efficient scalar instructions are generated from vector inputs. Added a new pattern to the instruction definitions and updating test cases to reflect the improved code generation.

- Added a new pattern in 'AArch64InstrFormats.td'
- Updated 'scvtf_f64i32_simple' test in 'fprcvt-cvtf.ll' to expect the `scvtf d0, s0` scalar instruction
- Removed outdated comment


>From 15dd6846787f365e73cf4a0a987c65d13795eb2f Mon Sep 17 00:00:00 2001
From: Amina Chabane <amina.chabane at arm.com>
Date: Mon, 11 Aug 2025 08:47:24 +0000
Subject: [PATCH] [AArch64] Correct SCVTF/UCVTF instructions for vector inputs

---
 llvm/lib/Target/AArch64/AArch64InstrFormats.td | 2 ++
 llvm/test/CodeGen/AArch64/fprcvt-cvtf.ll       | 8 +-------
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index ba7cbccc0bcd6..4e2c30a7aa7ee 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -5520,6 +5520,8 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
     let Inst{31} = 1; // 64-bit FPR flag
     let Inst{23-22} = 0b00; // 32-bit FPR flag
   }
+  def : Pat<(v1f64 (extract_subvector (v2f64 (node (v2i64 (sext (v2i32 V64:$Rn))))), (i64 0))),
+        (!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG V64:$Rn, ssub))>;
 
   def : Pat<(f16 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
           (!cast<Instruction>(NAME # HSr) (EXTRACT_SUBREG V128:$Rn, ssub))>;
diff --git a/llvm/test/CodeGen/AArch64/fprcvt-cvtf.ll b/llvm/test/CodeGen/AArch64/fprcvt-cvtf.ll
index 9da6f583cec01..254510abacdde 100644
--- a/llvm/test/CodeGen/AArch64/fprcvt-cvtf.ll
+++ b/llvm/test/CodeGen/AArch64/fprcvt-cvtf.ll
@@ -101,9 +101,7 @@ define double @scvtf_f64i32_neg(<4 x i32> %x) {
 define <1 x double> @scvtf_f64i32_simple(<1 x i32> %x) {
 ; CHECK-LABEL: scvtf_f64i32_simple:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sshll v0.2d, v0.2s, #0
-; CHECK-NEXT:    scvtf v0.2d, v0.2d
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    scvtf d0, s0
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-NO-FPRCVT-LABEL: scvtf_f64i32_simple:
@@ -202,10 +200,6 @@ define float @scvtf_f32i64_neg(<2 x i64> %x) {
  ret float %conv
 }
 
-; This test does not give the indended result of scvtf s0, d0
-; This is due to the input being loaded as a 2 item vector and
-; therefore using vector inputs that do not match the pattern
-; This test will be fixed in a future revision
 define <1 x float> @scvtf_f32i64_simple(<1 x i64> %x) {
 ; CHECK-LABEL: scvtf_f32i64_simple:
 ; CHECK:       // %bb.0: