[llvm] [AArch64][nfc] Remove duplicate [us]addl tests (PR #152664)
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 11 01:51:07 PDT 2025
https://github.com/c-rhodes updated https://github.com/llvm/llvm-project/pull/152664
>From bde4ca0b711a6d84a15d99453dd5a1faa8e12c38 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Thu, 7 Aug 2025 14:56:44 +0000
Subject: [PATCH 1/2] [AArch64][nfc] Remove duplicate [us]addl tests
in the following list we keep the first test:
- test_vaddl_[us]8, [us]addl8h, extadd[us]_v8i8_i16
- test_vaddl_[us]16, [us]addl4s, extadd[us]_v4i16_i32
- test_vaddl_[us]32, [us]addl2d, extadd[us]_v2i32_i64
---
llvm/test/CodeGen/AArch64/arm64-vadd.ll | 91 ------------------------
llvm/test/CodeGen/AArch64/neon-extadd.ll | 74 +------------------
2 files changed, 2 insertions(+), 163 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vadd.ll b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
index d982dbbb1f69b..f9263185f308e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
@@ -170,51 +170,6 @@ declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>) nounwind
declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-define <8 x i16> @saddl8h(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: saddl8h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = load <8 x i8>, ptr %B
- %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @saddl4s(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: saddl4s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
- %tmp1 = load <4 x i16>, ptr %A
- %tmp2 = load <4 x i16>, ptr %B
- %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @saddl2d(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: saddl2d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
- %tmp1 = load <2 x i32>, ptr %A
- %tmp2 = load <2 x i32>, ptr %B
- %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
define <8 x i16> @saddl2_8h(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECK-LABEL: saddl2_8h:
; CHECK: // %bb.0:
@@ -266,52 +221,6 @@ define <2 x i64> @saddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind {
ret <2 x i64> %add.i
}
-define <8 x i16> @uaddl8h(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: uaddl8h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = load <8 x i8>, ptr %B
- %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @uaddl4s(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: uaddl4s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
- %tmp1 = load <4 x i16>, ptr %A
- %tmp2 = load <4 x i16>, ptr %B
- %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @uaddl2d(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: uaddl2d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
- %tmp1 = load <2 x i32>, ptr %A
- %tmp2 = load <2 x i32>, ptr %B
- %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-
define <8 x i16> @uaddl2_8h(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECK-LABEL: uaddl2_8h:
; CHECK: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd.ll b/llvm/test/CodeGen/AArch64/neon-extadd.ll
index f5e566f49b91e..2c2a84bdf0067 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd.ll
@@ -2,30 +2,6 @@
; RUN: llc < %s -mtriple aarch64 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple aarch64 -o - -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-define <8 x i16> @extadds_v8i8_i16(<8 x i8> %s0, <8 x i8> %s1) {
-; CHECK-LABEL: extadds_v8i8_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
-entry:
- %s0s = sext <8 x i8> %s0 to <8 x i16>
- %s1s = sext <8 x i8> %s1 to <8 x i16>
- %m = add <8 x i16> %s0s, %s1s
- ret <8 x i16> %m
-}
-
-define <8 x i16> @extaddu_v8i8_i16(<8 x i8> %s0, <8 x i8> %s1) {
-; CHECK-LABEL: extaddu_v8i8_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
-entry:
- %s0s = zext <8 x i8> %s0 to <8 x i16>
- %s1s = zext <8 x i8> %s1 to <8 x i16>
- %m = add <8 x i16> %s0s, %s1s
- ret <8 x i16> %m
-}
-
define <16 x i16> @extadds_v16i8_i16(<16 x i8> %s0, <16 x i8> %s1) {
; CHECK-SD-LABEL: extadds_v16i8_i16:
; CHECK-SD: // %bb.0: // %entry
@@ -752,30 +728,6 @@ define <16 x i64> @extsubs_v16i16_i64(<16 x i16> %a, <16 x i16> %b) {
ret <16 x i64> %e
}
-define <4 x i32> @extadds_v4i16_i32(<4 x i16> %s0, <4 x i16> %s1) {
-; CHECK-LABEL: extadds_v4i16_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
-entry:
- %s0s = sext <4 x i16> %s0 to <4 x i32>
- %s1s = sext <4 x i16> %s1 to <4 x i32>
- %m = add <4 x i32> %s0s, %s1s
- ret <4 x i32> %m
-}
-
-define <4 x i32> @extaddu_v4i16_i32(<4 x i16> %s0, <4 x i16> %s1) {
-; CHECK-LABEL: extaddu_v4i16_i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
-entry:
- %s0s = zext <4 x i16> %s0 to <4 x i32>
- %s1s = zext <4 x i16> %s1 to <4 x i32>
- %m = add <4 x i32> %s0s, %s1s
- ret <4 x i32> %m
-}
-
define <8 x i32> @extadds_v8i16_i32(<8 x i16> %s0, <8 x i16> %s1) {
; CHECK-SD-LABEL: extadds_v8i16_i32:
; CHECK-SD: // %bb.0: // %entry
@@ -1024,30 +976,6 @@ entry:
ret <8 x i64> %m
}
-define <2 x i64> @extadds_v2i32_i64(<2 x i32> %s0, <2 x i32> %s1) {
-; CHECK-LABEL: extadds_v2i32_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
-entry:
- %s0s = sext <2 x i32> %s0 to <2 x i64>
- %s1s = sext <2 x i32> %s1 to <2 x i64>
- %m = add <2 x i64> %s0s, %s1s
- ret <2 x i64> %m
-}
-
-define <2 x i64> @extaddu_v2i32_i64(<2 x i32> %s0, <2 x i32> %s1) {
-; CHECK-LABEL: extaddu_v2i32_i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
-entry:
- %s0s = zext <2 x i32> %s0 to <2 x i64>
- %s1s = zext <2 x i32> %s1 to <2 x i64>
- %m = add <2 x i64> %s0s, %s1s
- ret <2 x i64> %m
-}
-
define <4 x i64> @extadds_v4i32_i64(<4 x i32> %s0, <4 x i32> %s1) {
; CHECK-SD-LABEL: extadds_v4i32_i64:
; CHECK-SD: // %bb.0: // %entry
@@ -1636,3 +1564,5 @@ entry:
%m = sub <16 x i32> %s0s, %s1s
ret <16 x i32> %m
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
>From 551523e15389d8f0ae7090151b642a70955d5921 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Mon, 11 Aug 2025 08:44:09 +0000
Subject: [PATCH 2/2] keep neon-extadd.ll
---
.../test/CodeGen/AArch64/arm64-neon-3vdiff.ll | 76 +------------------
llvm/test/CodeGen/AArch64/neon-extadd.ll | 74 +++++++++++++++++-
2 files changed, 74 insertions(+), 76 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll b/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
index 557fcbbb41961..22548e2735381 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
@@ -34,42 +34,6 @@ declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>)
declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>)
declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>)
-define <8 x i16> @test_vaddl_s8(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: test_vaddl_s8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = sext <8 x i8> %a to <8 x i16>
- %vmovl.i2.i = sext <8 x i8> %b to <8 x i16>
- %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i
- ret <8 x i16> %add.i
-}
-
-define <4 x i32> @test_vaddl_s16(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: test_vaddl_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = sext <4 x i16> %a to <4 x i32>
- %vmovl.i2.i = sext <4 x i16> %b to <4 x i32>
- %add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i
- ret <4 x i32> %add.i
-}
-
-define <2 x i64> @test_vaddl_s32(<2 x i32> %a, <2 x i32> %b) {
-; CHECK-LABEL: test_vaddl_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = sext <2 x i32> %a to <2 x i64>
- %vmovl.i2.i = sext <2 x i32> %b to <2 x i64>
- %add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i
- ret <2 x i64> %add.i
-}
-
define void @test_commutable_vaddl_s8(<8 x i8> %a, <8 x i8> %b, ptr %c) {
; CHECK-SD-LABEL: test_commutable_vaddl_s8:
; CHECK-SD: // %bb.0: // %entry
@@ -94,42 +58,6 @@ entry:
ret void
}
-define <8 x i16> @test_vaddl_u8(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: test_vaddl_u8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = zext <8 x i8> %a to <8 x i16>
- %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>
- %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i
- ret <8 x i16> %add.i
-}
-
-define <4 x i32> @test_vaddl_u16(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-LABEL: test_vaddl_u16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = zext <4 x i16> %a to <4 x i32>
- %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
- %add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i
- ret <4 x i32> %add.i
-}
-
-define <2 x i64> @test_vaddl_u32(<2 x i32> %a, <2 x i32> %b) {
-; CHECK-LABEL: test_vaddl_u32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
-; CHECK-NEXT: ret
-entry:
- %vmovl.i.i = zext <2 x i32> %a to <2 x i64>
- %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
- %add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i
- ret <2 x i64> %add.i
-}
-
define void @test_commutable_vaddl_u8(<8 x i8> %a, <8 x i8> %b, ptr %c) {
; CHECK-SD-LABEL: test_commutable_vaddl_u8:
; CHECK-SD: // %bb.0: // %entry
@@ -2940,9 +2868,9 @@ define <8 x i16> @cmplx_mul_combined_re_im(<8 x i16> noundef %a, i64 %scale.coer
; CHECK-GI-LABEL: cmplx_mul_combined_re_im:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: lsr x9, x0, #16
-; CHECK-GI-NEXT: adrp x8, .LCPI198_0
+; CHECK-GI-NEXT: adrp x8, .LCPI192_0
; CHECK-GI-NEXT: rev32 v4.8h, v0.8h
-; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI198_0]
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI192_0]
; CHECK-GI-NEXT: fmov d1, x9
; CHECK-GI-NEXT: dup v2.8h, v1.h[0]
; CHECK-GI-NEXT: sqneg v1.8h, v2.8h
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd.ll b/llvm/test/CodeGen/AArch64/neon-extadd.ll
index 2c2a84bdf0067..f5e566f49b91e 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd.ll
@@ -2,6 +2,30 @@
; RUN: llc < %s -mtriple aarch64 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple aarch64 -o - -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+define <8 x i16> @extadds_v8i8_i16(<8 x i8> %s0, <8 x i8> %s1) {
+; CHECK-LABEL: extadds_v8i8_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-NEXT: ret
+entry:
+ %s0s = sext <8 x i8> %s0 to <8 x i16>
+ %s1s = sext <8 x i8> %s1 to <8 x i16>
+ %m = add <8 x i16> %s0s, %s1s
+ ret <8 x i16> %m
+}
+
+define <8 x i16> @extaddu_v8i8_i16(<8 x i8> %s0, <8 x i8> %s1) {
+; CHECK-LABEL: extaddu_v8i8_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-NEXT: ret
+entry:
+ %s0s = zext <8 x i8> %s0 to <8 x i16>
+ %s1s = zext <8 x i8> %s1 to <8 x i16>
+ %m = add <8 x i16> %s0s, %s1s
+ ret <8 x i16> %m
+}
+
define <16 x i16> @extadds_v16i8_i16(<16 x i8> %s0, <16 x i8> %s1) {
; CHECK-SD-LABEL: extadds_v16i8_i16:
; CHECK-SD: // %bb.0: // %entry
@@ -728,6 +752,30 @@ define <16 x i64> @extsubs_v16i16_i64(<16 x i16> %a, <16 x i16> %b) {
ret <16 x i64> %e
}
+define <4 x i32> @extadds_v4i16_i32(<4 x i16> %s0, <4 x i16> %s1) {
+; CHECK-LABEL: extadds_v4i16_i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: ret
+entry:
+ %s0s = sext <4 x i16> %s0 to <4 x i32>
+ %s1s = sext <4 x i16> %s1 to <4 x i32>
+ %m = add <4 x i32> %s0s, %s1s
+ ret <4 x i32> %m
+}
+
+define <4 x i32> @extaddu_v4i16_i32(<4 x i16> %s0, <4 x i16> %s1) {
+; CHECK-LABEL: extaddu_v4i16_i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: ret
+entry:
+ %s0s = zext <4 x i16> %s0 to <4 x i32>
+ %s1s = zext <4 x i16> %s1 to <4 x i32>
+ %m = add <4 x i32> %s0s, %s1s
+ ret <4 x i32> %m
+}
+
define <8 x i32> @extadds_v8i16_i32(<8 x i16> %s0, <8 x i16> %s1) {
; CHECK-SD-LABEL: extadds_v8i16_i32:
; CHECK-SD: // %bb.0: // %entry
@@ -976,6 +1024,30 @@ entry:
ret <8 x i64> %m
}
+define <2 x i64> @extadds_v2i32_i64(<2 x i32> %s0, <2 x i32> %s1) {
+; CHECK-LABEL: extadds_v2i32_i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
+; CHECK-NEXT: ret
+entry:
+ %s0s = sext <2 x i32> %s0 to <2 x i64>
+ %s1s = sext <2 x i32> %s1 to <2 x i64>
+ %m = add <2 x i64> %s0s, %s1s
+ ret <2 x i64> %m
+}
+
+define <2 x i64> @extaddu_v2i32_i64(<2 x i32> %s0, <2 x i32> %s1) {
+; CHECK-LABEL: extaddu_v2i32_i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
+; CHECK-NEXT: ret
+entry:
+ %s0s = zext <2 x i32> %s0 to <2 x i64>
+ %s1s = zext <2 x i32> %s1 to <2 x i64>
+ %m = add <2 x i64> %s0s, %s1s
+ ret <2 x i64> %m
+}
+
define <4 x i64> @extadds_v4i32_i64(<4 x i32> %s0, <4 x i32> %s1) {
; CHECK-SD-LABEL: extadds_v4i32_i64:
; CHECK-SD: // %bb.0: // %entry
@@ -1564,5 +1636,3 @@ entry:
%m = sub <16 x i32> %s0s, %s1s
ret <16 x i32> %m
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
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