[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

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@@ -1608,6 +1612,42 @@ void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
   Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
 }
 
+void DAGTypeLegalizer::SplitVecRes_LOOP_DEPENDENCE_MASK(SDNode *N, SDValue &Lo,
+                                                        SDValue &Hi) {
+  EVT EltVT;
+  switch (N->getConstantOperandVal(2)) {
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sdesmalen-arm wrote:

Why is the element size relevant for splitting?

https://github.com/llvm/llvm-project/pull/117007