[llvm] [ARM] Have IntCCToARMCC handle PL or MI (NFC) (PR #150247)
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Tue Aug 5 11:11:09 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/150247
>From 4da61aeab5d56807b7fe628ffbe7d42e2394dbc9 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Wed, 23 Jul 2025 12:00:21 -0400
Subject: [PATCH 1/3] [ARM] Have IntCCToARMCC handle PL or MI (NFC)
Do not know if it is safe for the other uses to use PL or MI (not sure which RHS they use) so for now they are false.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 33 +++++++++----------------
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 65d1c4e2d6515..16d06fa0a95a9 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -2020,14 +2020,17 @@ static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
}
/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
-static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
+static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC, SDValue RHS,
+ bool canUsePLOrMI = true) {
switch (CC) {
default: llvm_unreachable("Unknown condition code!");
case ISD::SETNE: return ARMCC::NE;
case ISD::SETEQ: return ARMCC::EQ;
case ISD::SETGT: return ARMCC::GT;
- case ISD::SETGE: return ARMCC::GE;
- case ISD::SETLT: return ARMCC::LT;
+ case ISD::SETGE:
+ return canUsePLOrMI && isNullConstant(RHS) ? ARMCC::PL : ARMCC::GE;
+ case ISD::SETLT:
+ return canUsePLOrMI && isNullConstant(RHS) ? ARMCC::MI : ARMCC::LT;
case ISD::SETLE: return ARMCC::LE;
case ISD::SETUGT: return ARMCC::HI;
case ISD::SETUGE: return ARMCC::HS;
@@ -4924,22 +4927,7 @@ SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
return Shift.getValue(1);
}
- ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
-
- // If the RHS is a constant zero then the V (overflow) flag will never be
- // set. This can allow us to simplify GE to PL or LT to MI, which can be
- // simpler for other passes (like the peephole optimiser) to deal with.
- if (isNullConstant(RHS)) {
- switch (CondCode) {
- default: break;
- case ARMCC::GE:
- CondCode = ARMCC::PL;
- break;
- case ARMCC::LT:
- CondCode = ARMCC::MI;
- break;
- }
- }
+ ARMCC::CondCodes CondCode = IntCCToARMCC(CC, RHS);
ARMISD::NodeType CompareType;
switch (CondCode) {
@@ -5611,7 +5599,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
TrueVal.getValueType() == MVT::f32 ||
TrueVal.getValueType() == MVT::f64)) {
- ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
+ ARMCC::CondCodes CondCode = IntCCToARMCC(CC, RHS, false);
if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
@@ -5768,7 +5756,7 @@ ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
expandf64Toi32(RHS, DAG, RHS1, RHS2);
LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
- ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
+ ARMCC::CondCodes CondCode = IntCCToARMCC(CC, RHS2, false);
ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
return DAG.getNode(ARMISD::BCC_i64, dl, MVT::Other, Ops);
@@ -7034,7 +7022,8 @@ static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
SDValue ARMcc = DAG.getConstant(
- IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
+ IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get(), RHS, false), DL,
+ MVT::i32);
return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
Cmp.getValue(1));
}
>From a0c110f87d977f36a16b6670a93fddab36f0cda7 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 5 Aug 2025 14:08:52 -0400
Subject: [PATCH 2/3] Simplify
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 16d06fa0a95a9..268bd23d9b0b5 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -2020,17 +2020,16 @@ static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
}
/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
-static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC, SDValue RHS,
- bool canUsePLOrMI = true) {
+static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC, SDValue RHS = {}) {
switch (CC) {
default: llvm_unreachable("Unknown condition code!");
case ISD::SETNE: return ARMCC::NE;
case ISD::SETEQ: return ARMCC::EQ;
case ISD::SETGT: return ARMCC::GT;
case ISD::SETGE:
- return canUsePLOrMI && isNullConstant(RHS) ? ARMCC::PL : ARMCC::GE;
+ return (RHS && isNullConstant(RHS)) ? ARMCC::PL : ARMCC::GE;
case ISD::SETLT:
- return canUsePLOrMI && isNullConstant(RHS) ? ARMCC::MI : ARMCC::LT;
+ return (RHS && isNullConstant(RHS)) ? ARMCC::MI : ARMCC::LT;
case ISD::SETLE: return ARMCC::LE;
case ISD::SETUGT: return ARMCC::HI;
case ISD::SETUGE: return ARMCC::HS;
@@ -5599,7 +5598,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
TrueVal.getValueType() == MVT::f32 ||
TrueVal.getValueType() == MVT::f64)) {
- ARMCC::CondCodes CondCode = IntCCToARMCC(CC, RHS, false);
+ ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
@@ -5756,7 +5755,7 @@ ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
expandf64Toi32(RHS, DAG, RHS1, RHS2);
LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
- ARMCC::CondCodes CondCode = IntCCToARMCC(CC, RHS2, false);
+ ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
return DAG.getNode(ARMISD::BCC_i64, dl, MVT::Other, Ops);
@@ -7022,7 +7021,7 @@ static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
SDValue ARMcc = DAG.getConstant(
- IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get(), RHS, false), DL,
+ IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL,
MVT::i32);
return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
Cmp.getValue(1));
>From 014abd0e778df8c7bf8277301da73c480c69d84e Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 5 Aug 2025 14:11:00 -0400
Subject: [PATCH 3/3] Fix formatting
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 268bd23d9b0b5..840bd1c28af55 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -7021,8 +7021,7 @@ static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
SDValue ARMcc = DAG.getConstant(
- IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL,
- MVT::i32);
+ IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
Cmp.getValue(1));
}
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