[llvm] [CodeGen] MachineVerifier to check early-clobber constraint (PR #151421)

via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 4 10:36:54 PDT 2025


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Abhay Kanhere (AbhayKanhere)

<details>
<summary>Changes</summary>


Currently MachineVerifier is missing verifying early-clobber operand constraint. 
The only other machine operand constraint -  TiedTo is already verified.

---
Full diff: https://github.com/llvm/llvm-project/pull/151421.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/MachineVerifier.cpp (+7) 
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (+1) 


``````````diff
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 01703fe09b79a..ebef1c9034f4a 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2325,6 +2325,13 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
       report("Missing mayStore flag", MI);
   }
 
+  // Verify earlyClobber def operand
+  if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
+    if (!MI->getOperand(0).isReg())
+      report("Early clobber must be a register", MI);
+    if (!MI->getOperand(0).isEarlyClobber())
+      report("Missing earlyClobber flag", MI);
+  }
   // Debug values must not have a slot index.
   // Other instructions must have one, unless they are inside a bundle.
   if (LiveInts) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 1a63c48e3666c..8a6ef89a4a062 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -584,6 +584,7 @@ bool AMDGPUInstructionSelector::selectG_AMDGPU_MAD_64_32(
   I.setDesc(TII.get(Opc));
   I.addOperand(*MF, MachineOperand::CreateImm(0));
   I.addImplicitDefUseOperands(*MF);
+  I.getOperand(0).setIsEarlyClobber(true);
   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 }
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/151421


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