[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

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@@ -5084,6 +5094,57 @@ SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
 
 static MVT getSVEContainerType(EVT ContentTy);
 
+SDValue
+AArch64TargetLowering::LowerLOOP_DEPENDENCE_MASK(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  uint64_t EltSize = Op.getConstantOperandVal(2);
+  bool IsWriteAfterRead = Op.getOpcode() == ISD::LOOP_DEPENDENCE_WAR_MASK;
+  unsigned Opcode =
+      IsWriteAfterRead ? AArch64ISD::WHILEWR : AArch64ISD::WHILERW;
+  EVT VT = Op.getValueType();
+  MVT SimpleVT = VT.getSimpleVT();
+  // Make sure that the promoted mask size and element size match
+  switch (EltSize) {
+  case 1:
+    assert((SimpleVT == MVT::v16i8 || SimpleVT == MVT::nxv16i1) &&
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sdesmalen-arm wrote:

nit: you can just compare with `VT` directly, removing the need for `SimpleVT`.

https://github.com/llvm/llvm-project/pull/117007