[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

================
@@ -6317,6 +6390,53 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getNode(AArch64ISD::USDOT, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
   }
+  case Intrinsic::loop_dependence_war_mask:
+  case Intrinsic::loop_dependence_raw_mask: {
+    unsigned IntrinsicID = 0;
+    uint64_t EltSize = Op.getOperand(3)->getAsZExtVal();
+    bool IsWriteAfterRead = Op.getOperand(4)->getAsZExtVal() == 1;
+    switch (EltSize) {
+    case 1:
+      IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_b
+                                     : Intrinsic::aarch64_sve_whilerw_b;
+      break;
+    case 2:
+      IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_h
+                                     : Intrinsic::aarch64_sve_whilerw_h;
+      break;
+    case 4:
+      IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_s
+                                     : Intrinsic::aarch64_sve_whilerw_s;
+      break;
+    case 8:
+      IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_d
+                                     : Intrinsic::aarch64_sve_whilerw_d;
+      break;
+    default:
+      llvm_unreachable("Unexpected element size for get.alias.lane.mask");
+      break;
+    }
+    SDValue ID = DAG.getTargetConstant(IntrinsicID, dl, MVT::i64);
+
+    EVT VT = Op.getValueType();
+    if (VT.isScalableVector())
+      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, ID, Op.getOperand(1),
+                         Op.getOperand(2));
+
+    // We can use the SVE whilewr/whilerw instruction to lower this
+    // intrinsic by creating the appropriate sequence of scalable vector
+    // operations and then extracting a fixed-width subvector from the scalable
+    // vector.
+
+    EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
+    EVT WhileVT = ContainerVT.changeElementType(MVT::i1);
+
+    SDValue Mask = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, WhileVT, ID,
+                               Op.getOperand(1), Op.getOperand(2));
+    SDValue MaskAsInt = DAG.getNode(ISD::SIGN_EXTEND, dl, ContainerVT, Mask);
+    return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, MaskAsInt,
+                       DAG.getVectorIdxConstant(0, dl));
+  }
----------------
sdesmalen-arm wrote:

This code can be removed, because a `loop.dependence.war.mask` is always transformed into a `ISD::LOOP_DEPENDENCE_WAR_MASK` by SelectionDAG and so it should never get here.

https://github.com/llvm/llvm-project/pull/117007