[llvm] [AMDGPU] Legalize 64bit elements for BUILD_VECTOR on gfx942 (PR #145052)

[Janek van Oirschot via llvm-commits]

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@@ -16037,6 +16165,14 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
     return performInsertVectorEltCombine(N, DCI);
   case ISD::FP_ROUND:
     return performFPRoundCombine(N, DCI);
+  case ISD::BITCAST: {
+    // Avoid undoing build_vector with 64b elements if subtarget supports 64b
+    // movs (i.e., avoid inf loop through combines).
+    const GCNSubtarget *ST = getSubtarget();
+    if (ST->hasMovB64())
+      return SDValue();
+    break;
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JanekvO wrote:

I couldn't do an obvious `isOperationLegal` check. Particularly for the combine `v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)` which I'm trying to avoid as 64b can be directly materialized through [v/s]_mov_b64. I think it would have to boil down to gating it on `hasMovB64()` again in `AMDGPUTargetLowering::PerformDAGCombine`'s `BITCAST` combine.

https://github.com/llvm/llvm-project/pull/145052