[llvm] [AArch64] Support symmetric complex deinterleaving with higher factors (PR #151295)

[David Sherwood via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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david-arm wrote:

Yeah so the pass already handles `@simple_symmetric_muladd2`, but I didn't add support for the fixed-width patterns in `@simple_symmetric_muladd4` mainly because I'd expect the VectorCombine pass to have already removed the shuffles before we reach the complex deinterleaving pass. However, if we find cases where actually it would be useful to support fixed-width vectors it should be easy enough to add.

https://github.com/llvm/llvm-project/pull/151295