[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Paul Walker via llvm-commits]

================
@@ -24026,6 +24026,66 @@ static SDValue combineBoolVectorAndTruncateStore(SelectionDAG &DAG,
                       Store->getMemOperand());
 }
 
+// Combine store (fp_to_int X) with to use vector semantics around the
+// conversion when NEON is available.
+static SDValue combineStoreValueFPToInt(StoreSDNode *ST,
+                                        TargetLowering::DAGCombinerInfo &DCI,
+                                        SelectionDAG &DAG,
+                                        const AArch64Subtarget *Subtarget) {
+  // Limit to post-legalization in order to avoid peeling truncating stores.
+  if (DCI.isBeforeLegalize())
+    return {};
+  if (!Subtarget->isNeonAvailable())
+    return {};
+  // Source operand is already a vector.
+  SDValue Value = ST->getValue();
+  if (Value.getValueType().isVector())
+    return {};
+
+  // Look through potential assertions.
+  while (Value->isAssert())
+    Value = Value.getOperand(0);
+
+  if (Value.getOpcode() != ISD::FP_TO_SINT &&
+      Value.getOpcode() != ISD::FP_TO_UINT)
+    return {};
+  if (!Value->hasOneUse())
+    return {};
+
+  SDValue FPSrc = Value.getOperand(0);
+  EVT SrcVT = FPSrc.getValueType();
+  assert(!SrcVT.isVector());
----------------
paulwalker-arm wrote:

This assert is not necessary. You don't need to verify the DAG is valid.

That said, when looking at the tests and isel patterns you only care about floats and doubles? Half and bfloat support usually requires more complexity so perhaps change this to:
```
if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
  return SDValue();
```

https://github.com/llvm/llvm-project/pull/147707