[llvm] [X86][GlobalISel] Improve carry value selection (PR #146586)

[Evgenii Kudriashov via llvm-commits]

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@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -global-isel=1 -global-isel-abort=1 | FileCheck %s
+
+; Issue #120029
+define i16 @use_carry_bit(i16 %2) {
+; CHECK-LABEL: use_carry_bit:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movw $1, %ax
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    addw %di, %ax
+; CHECK-NEXT:    setb %cl
+; CHECK-NEXT:    andl $1, %ecx
+; CHECK-NEXT:    cmovnew %di, %ax
+; CHECK-NEXT:    retq
+  %4 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 %2, i16 1)
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e-kud wrote:

Thanks! Fixed.

https://github.com/llvm/llvm-project/pull/146586