[llvm] [RISCV] Update SpacemiT-X60 vector mask instructions latencies (PR #150644)

[Min-Yih Hsu via llvm-commits]

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@@ -650,13 +650,20 @@ foreach mx = SchedMxListFWRed in {
 foreach mx = SchedMxList in {
   defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;
 
-  defm "" : LMULWriteResMX<"WriteVMALUV", [SMX60_VIEU], mx, IsWorstCase>;
-  defm "" : LMULWriteResMX<"WriteVMPopV", [SMX60_VIEU], mx, IsWorstCase>;
-  defm "" : LMULWriteResMX<"WriteVMFFSV", [SMX60_VIEU], mx, IsWorstCase>;
-  defm "" : LMULWriteResMX<"WriteVMSFSV", [SMX60_VIEU], mx, IsWorstCase>;
+  let Latency = 4, ReleaseAtCycles = [4] in  {
+    defm "" : LMULWriteResMX<"WriteVMALUV", [SMX60_VIEU], mx, IsWorstCase>;
+    defm "" : LMULWriteResMX<"WriteVMSFSV", [SMX60_VIEU], mx, IsWorstCase>;
+  }
+
+  let Latency = 6, ReleaseAtCycles = [6] in  {
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mshockwave wrote:

A question similar to one that I asked in another previous PR: are these instructions not pipelined?

https://github.com/llvm/llvm-project/pull/150644