[llvm] [RISCV] Update SpacemiT-X60 vector mask instructions latencies (PR #150644)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 25 09:12:19 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Mikhail R. Gadelha (mikhailramalho)
<details>
<summary>Changes</summary>
This PR adds hardware-measured latencies for all instructions defined in Section 15 of the RVV specification: "Vector Mask Instructions" to the SpacemiT-X60 scheduling model.
---
Patch is 239.74 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/150644.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td (+13-6)
- (modified) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s (+603-603)
- (modified) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s (+45-45)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index bf23812c992ba..348fe949c1250 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -650,13 +650,20 @@ foreach mx = SchedMxListFWRed in {
foreach mx = SchedMxList in {
defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;
- defm "" : LMULWriteResMX<"WriteVMALUV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVMPopV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVMFFSV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVMSFSV", [SMX60_VIEU], mx, IsWorstCase>;
+ let Latency = 4, ReleaseAtCycles = [4] in {
+ defm "" : LMULWriteResMX<"WriteVMALUV", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [SMX60_VIEU], mx, IsWorstCase>;
+ }
+
+ let Latency = 6, ReleaseAtCycles = [6] in {
+ defm "" : LMULWriteResMX<"WriteVMPopV", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMFFSV", [SMX60_VIEU], mx, IsWorstCase>;
+ }
- defm "" : LMULWriteResMX<"WriteVIotaV", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIdxV", [SMX60_VIEU], mx, IsWorstCase>;
+ let Latency = Get4816Latency<mx>.c, ReleaseAtCycles = [4] in {
+ defm "" : LMULWriteResMX<"WriteVIotaV", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIdxV", [SMX60_VIEU], mx, IsWorstCase>;
+ }
}
// 16. Vector Permutation Instructions
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
index ce1ade0f143af..0cc44cf13ad49 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
@@ -642,607 +642,607 @@ vfirst.m x8, v8
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMAND_MM vmmv.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMNAND_MM vmnot.m v8, v8
# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 1 1.00 1 SMX60_VIEU VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT:...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/150644
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