[llvm] [TableGen] Strengthen check for what operands can be an immediate in CompressInstEmitter. (PR #150568)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tablegen

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

Registers can be represented by RegisterOperand, not just RegisterClass. Instead of trying to block certain classes, only allow Operand.

---
Full diff: https://github.com/llvm/llvm-project/pull/150568.diff


1 Files Affected:

- (modified) llvm/utils/TableGen/CompressInstEmitter.cpp (+1-1) 


``````````diff
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index 4665a964bd9e7..b2429664783b9 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -269,7 +269,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
         OperandMap[OpNo].Kind = OpData::Operand;
       } else if (const auto *II = dyn_cast<IntInit>(Dag->getArg(DAGOpNo))) {
         // Validate that corresponding instruction operand expects an immediate.
-        if (OpndRec->isSubClassOf("RegisterClass"))
+        if (!OpndRec->isSubClassOf("Operand"))
           PrintFatalError(Rec->getLoc(), "Error in Dag '" + Dag->getAsString() +
                                              "' Found immediate: '" +
                                              II->getAsString() +

``````````

</details>


https://github.com/llvm/llvm-project/pull/150568