[llvm] [AMDGPU] Add option to prevent insns straddling half cache-line boundaries (PR #150239)

[Matt Arsenault via llvm-commits]

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@@ -525,6 +525,12 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
   void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;
 
 public:
+  // Current known instruction alignment and offset in bytes.
+  // Used to prevent instructions from straddling half cache-line boundaries
+  // for performance.
+  unsigned Alignment = 1;
+  unsigned Offset = 0;
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arsenm wrote:

This doesn't belong in MachineFunctionInfo. No per-pass state should ever be here

https://github.com/llvm/llvm-project/pull/150239