[llvm] [RISCV][TTI] Enable masked interleave vectorization (PR #150074)

[Philip Reames via llvm-commits]

================
@@ -979,12 +979,14 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
     Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
     bool UseMaskForCond, bool UseMaskForGaps) const {
 
-  // The interleaved memory access pass will lower interleaved memory ops (i.e
-  // a load and store followed by a specific shuffle) to vlseg/vsseg
-  // intrinsics.
-  if (!UseMaskForCond && !UseMaskForGaps &&
+  auto *VTy = cast<VectorType>(VecTy);
+
+  // The interleaved memory access pass will lower (de)interleave ops combined
+  // with an adjacent appropriate memory to vlseg/vsseg intrinsics.  We
+  // currently only support masking for the scalable path. vlseg/vsseg only
+  // support masking per-iteration (i.e. condition), not per-segment (i.e. gap).
+  if ((VTy->isScalableTy() || !UseMaskForCond) && !UseMaskForGaps &&
----------------
preames wrote:

Luke is correct here.  I am actively working on fully supporting the shuffle path with masked.load/store, but we're not there yet.  The next change is https://github.com/llvm/llvm-project/pull/150241, and we've got at least one more needed after that before we could reasonable enable fixed vectors by default.  

https://github.com/llvm/llvm-project/pull/150074