[llvm] [RISCV][TTI] Enable masked interleave vectorization (PR #150074)

[Mel Chen via llvm-commits]

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@@ -979,12 +979,14 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
     Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
     bool UseMaskForCond, bool UseMaskForGaps) const {
 
-  // The interleaved memory access pass will lower interleaved memory ops (i.e
-  // a load and store followed by a specific shuffle) to vlseg/vsseg
-  // intrinsics.
-  if (!UseMaskForCond && !UseMaskForGaps &&
+  auto *VTy = cast<VectorType>(VecTy);
+
+  // The interleaved memory access pass will lower (de)interleave ops combined
+  // with an adjacent appropriate memory to vlseg/vsseg intrinsics.  We
+  // currently only support masking for the scalable path. vlseg/vsseg only
+  // support masking per-iteration (i.e. condition), not per-segment (i.e. gap).
+  if ((VTy->isScalableTy() || !UseMaskForCond) && !UseMaskForGaps &&
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Mel-Chen wrote:

Ah, I see. Then I think it does make sense to initially limit support to scalable only. Thanks!

https://github.com/llvm/llvm-project/pull/150074