[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

Thanks for continuing to dig down on this.  My immediate thoughts are:
* Can you add isel patterns for the 2-element vector cases where the operand is an insert into undef and match them to the scalar instructions?
* Or if this is problematic, perhaps it's worth introducing a dedicated AArch64ISD nodes for in-reg fp-int conversion so the input and result types remain scalar floating point types?

https://github.com/llvm/llvm-project/pull/147707