[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Guy David via llvm-commits]

guy-david wrote:

We can avoid legalization issues if we use 2-element vectors instead of single element ones as shown here: 89d044ea4cb4aaf8269074034e6f6a8c4cac1816. The drawback is that now the core has to operate on twice the data because the emitted code has `fcvtzs v0.2d, v0.2d` instead of just `fcvtzs d0, d0`.

https://github.com/llvm/llvm-project/pull/147707