[llvm] [LLVM][CodeGen][SVE] Don't combine shifts at the expense of addressing modes. (PR #149873)

[Ricardo Jesus via llvm-commits]

================
@@ -18010,10 +18010,17 @@ bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
       unsigned ShlAmt = C2->getZExtValue();
       if (auto ShouldADD = *N->user_begin();
           ShouldADD->getOpcode() == ISD::ADD && ShouldADD->hasOneUse()) {
-        if (auto ShouldLOAD = dyn_cast<LoadSDNode>(*ShouldADD->user_begin())) {
-          unsigned ByteVT = ShouldLOAD->getMemoryVT().getSizeInBits() / 8;
-          if ((1ULL << ShlAmt) == ByteVT &&
-              isIndexedLoadLegal(ISD::PRE_INC, ShouldLOAD->getMemoryVT()))
+        if (auto Load = dyn_cast<LoadSDNode>(*ShouldADD->user_begin())) {
+          TypeSize Size = Load->getMemoryVT().getSizeInBits();
+          // NOTE: +3 to account for bytes->bits transition.
+          if (TypeSize::getFixed(1ULL << (ShlAmt + 3)) == Size &&
----------------
rj-jesus wrote:

Could use 8ULL if you want to avoid the +3 increment.

https://github.com/llvm/llvm-project/pull/149873