[llvm] [LLVM][CodeGen][SVE] Don't combine shifts at the expense of addressing modes. (PR #149873)

[Paul Walker via llvm-commits]

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@@ -18011,9 +18011,10 @@ bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
       if (auto ShouldADD = *N->user_begin();
           ShouldADD->getOpcode() == ISD::ADD && ShouldADD->hasOneUse()) {
         if (auto ShouldLOAD = dyn_cast<LoadSDNode>(*ShouldADD->user_begin())) {
-          unsigned ByteVT = ShouldLOAD->getMemoryVT().getSizeInBits() / 8;
+          unsigned ByteVT = ShouldLOAD->getMemoryVT().getScalarSizeInBits() / 8;
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paulwalker-arm wrote:

I've added the missing test case and rewritten the logic to maintain the existing code, albeit making it TypeSize safe, and extracted the SVE use case into a separate check.  Given the slight restructuring I figured I may as well remove the implicit truncation when converting the bit size to bytes.  I doubt this has or will affect anything but figured it is better to ensure there's an exact match.

https://github.com/llvm/llvm-project/pull/149873