[llvm] [AArch64][CodeGen] Optimize register zero initialization in svsub_x (PR #149840)

[David Green via llvm-commits]

davemgreen wrote:

I believe this should trigger: https://github.com/llvm/llvm-project/blob/579a80784d43f4c21ac4ee2df221ba4f3b98fd70/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp#L2790

You will need to run `opt -passes=instcombine`, it is not usually ran as part of the backend.

https://github.com/llvm/llvm-project/pull/149840