[llvm] [AMDGPU] Generate waterfall for calls with SGPR(inreg) argument (PR #146997)

[Shilei Tian via llvm-commits]

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@@ -1128,6 +1169,45 @@ void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
   }
 }
 
+void SIFixSGPRCopies::lowerPysicalSGPRInsts(MachineFunction &MF) {
+  for (auto &Entry : WaterFalls) {
+    MachineInstr *MI = Entry.first;
+    const V2PhysSCopyInfo &Info = Entry.second;
+    assert((Info.MOs.size() != 0 && Info.SGPRs.size() == Info.MOs.size()) &&
+           "Error in MOs or SGPRs size.");
+
+    if (MI->getOpcode() == AMDGPU::SI_CALL_ISEL) {
+      // Move everything between ADJCALLSTACKUP and ADJCALLSTACKDOWN and
+      // following copies, we also need to move copies from and to physical
+      // registers into the loop block.
+      unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
+      unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
+
+      // Also move the copies to physical registers into the loop block
+      MachineBasicBlock &MBB = *MI->getParent();
+      MachineBasicBlock::iterator Start(MI);
+      while (Start->getOpcode() != FrameSetupOpcode)
+        --Start;
+      MachineBasicBlock::iterator End(MI);
+      while (End->getOpcode() != FrameDestroyOpcode)
+        ++End;
+
+      // Also include following copies of the return value
+      ++End;
+      while (End != MBB.end() && End->isCopy() && End->getOperand(1).isReg() &&
+             MI->definesRegister(End->getOperand(1).getReg(), TRI))
+        ++End;
+
+      llvm::loadMBUFScalarOperandsFromVGPR(*TII, *MI, Info.MOs, MDT, Start, End,
+                                           Info.SGPRs);
+    }
+  }
+  // Avoid some O0 tests where no use of COPY to SGPR
+  if (!WaterFalls.empty())
+    for (auto &Entry : V2PhySCopiesToErase)
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shiltian wrote:

no auto

https://github.com/llvm/llvm-project/pull/146997