[llvm] [AMDGPU] Generate waterfall for calls with SGPR(inreg) argument (PR #146997)

[Matt Arsenault via llvm-commits]

================
@@ -76,3 +193,66 @@ define void @indirect_tail_call_i32_inreg_divergent(i32 %vgpr) {
   tail call void %fptr(i32 inreg %vgpr)
   ret void
 }
+
+declare void @user(ptr addrspace(5))
+
+define amdgpu_kernel void @v_multiple_frame_indexes_literal_offsets() #0 {
+; CHECK-LABEL: v_multiple_frame_indexes_literal_offsets:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT:    s_add_u32 s0, s0, s17
+; CHECK-NEXT:    v_mov_b32_e32 v3, 8
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; CHECK-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
+; CHECK-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
+; CHECK-NEXT:    s_addc_u32 s1, s1, 0
+; CHECK-NEXT:    s_mov_b32 s33, s16
+; CHECK-NEXT:    s_mov_b32 s50, s15
+; CHECK-NEXT:    s_mov_b32 s51, s14
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
+; CHECK-NEXT:    s_mov_b64 s[48:49], s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
+; CHECK-NEXT:    v_or3_b32 v31, v0, v1, v2
+; CHECK-NEXT:    s_movk_i32 s32, 0x400
+; CHECK-NEXT:    s_mov_b64 s[4:5], exec
+; CHECK-NEXT:  .LBB2_1: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    v_readfirstlane_b32 s15, v3
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v3
+; CHECK-NEXT:    s_and_saveexec_b64 s[52:53], vcc
+; CHECK-NEXT:    s_getpc_b64 s[4:5]
+; CHECK-NEXT:    s_add_u32 s4, s4, user at gotpcrel32@lo+4
+; CHECK-NEXT:    s_addc_u32 s5, s5, user at gotpcrel32@hi+12
+; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[4:5], 0x0
+; CHECK-NEXT:    s_mov_b64 s[4:5], s[48:49]
+; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
+; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
+; CHECK-NEXT:    s_mov_b64 s[10:11], s[34:35]
+; CHECK-NEXT:    s_mov_b32 s12, s51
+; CHECK-NEXT:    s_mov_b32 s13, s50
+; CHECK-NEXT:    s_mov_b32 s14, s33
+; CHECK-NEXT:    s_mov_b32 s0, s15
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT:    ; implicit-def: $vgpr3
+; CHECK-NEXT:    ; implicit-def: $vgpr31
+; CHECK-NEXT:    s_xor_b64 exec, exec, s[52:53]
+; CHECK-NEXT:    s_cbranch_execnz .LBB2_1
+; CHECK-NEXT:  ; %bb.2:
+; CHECK-NEXT:    s_endpgm
+  %vgpr = call i32 @llvm.amdgcn.workitem.id.x()
+  %alloca0 = alloca [2 x i32], align 8, addrspace(5)
+  %alloca1 = alloca i32, align 4, addrspace(5)
+  %cmp = icmp eq i32 %vgpr, 0
+  %select = select i1 %cmp, ptr addrspace(5) %alloca0, ptr addrspace(5) %alloca1
+  call void @user(ptr addrspace(5) inreg %select)
+  ret void
+}
+
----------------
arsenm wrote:

Should have more tests with more argument types. In particular I would like to check that multiple operands are handled correctly, where we only iterate per unique combination of inputs across all lanes 

https://github.com/llvm/llvm-project/pull/146997