[llvm] [AArch64] Add zero cycle register move statistics (PR #149033)
Tomer Shafir via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 16 01:07:38 PDT 2025
https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/149033
This patch adds zero cycle register move counters per register class, which improves the visiblity of this aspect of lowering at compile time.
>From a271841c4a1221e793b951c57c8067b7b7c1ae17 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Wed, 16 Jul 2025 11:04:56 +0300
Subject: [PATCH] [AArch64] Add zero cycle register move statistics
This patch adds zero cycle register move counters per register class, which improves the visiblity of this aspect of lowering at compile time.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 50 +++++++++++++++++++-
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 5420545cc3cec..4082c86ccd912 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -60,9 +61,22 @@
using namespace llvm;
+#define DEBUG_TYPE "aarch64-instr-info"
+
#define GET_INSTRINFO_CTOR_DTOR
#include "AArch64GenInstrInfo.inc"
+STATISTIC(NumZeroCycleRegMoveGPR32,
+ "Number of lowered zero cycle register moves of GPR32 class");
+STATISTIC(NumZeroCycleRegMoveGPR64,
+ "Number of lowered zero cycle register moves of GPR64 class");
+STATISTIC(NumZeroCycleRegMoveFPR128,
+ "Number of lowered zero cycle register moves of FPR128 class");
+STATISTIC(NumZeroCycleRegMoveFPR64,
+ "Number of lowered zero cycle register moves of FPR64 class");
+STATISTIC(NumZeroCycleRegMoveFPR32,
+ "Number of lowered zero cycle register moves of FPR32 class");
+
static cl::opt<unsigned>
CBDisplacementBits("aarch64-cb-offset-bits", cl::Hidden, cl::init(9),
cl::desc("Restrict range of CB instructions (DEBUG)"));
@@ -5061,11 +5075,15 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
+ ++NumZeroCycleRegMoveGPR64;
} else {
BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
+ if (Subtarget.hasZeroCycleRegMoveGPR32()) {
+ ++NumZeroCycleRegMoveGPR32;
+ }
}
} else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGP()) {
BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
@@ -5087,11 +5105,15 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(AArch64::XZR)
.addReg(SrcRegX, RegState::Undef)
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
+ ++NumZeroCycleRegMoveGPR64;
} else {
// Otherwise, expand to ORR WZR.
BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
.addReg(AArch64::WZR)
.addReg(SrcReg, getKillRegState(KillSrc));
+ if (Subtarget.hasZeroCycleRegMoveGPR32()) {
+ ++NumZeroCycleRegMoveGPR32;
+ }
}
}
return;
@@ -5189,6 +5211,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
+ if (Subtarget.hasZeroCycleRegMoveGPR64()) {
+ ++NumZeroCycleRegMoveGPR64;
+ }
} else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGP()) {
BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
.addImm(0)
@@ -5198,6 +5223,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
.addReg(AArch64::XZR)
.addReg(SrcReg, getKillRegState(KillSrc));
+ if (Subtarget.hasZeroCycleRegMoveGPR64()) {
+ ++NumZeroCycleRegMoveGPR64;
+ }
}
return;
}
@@ -5284,11 +5312,14 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(AArch64::Z0 + (DestReg - AArch64::Q0), RegState::Define)
.addReg(AArch64::Z0 + (SrcReg - AArch64::Q0))
.addReg(AArch64::Z0 + (SrcReg - AArch64::Q0));
- else if (Subtarget.isNeonAvailable())
+ else if (Subtarget.isNeonAvailable()) {
BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
.addReg(SrcReg)
.addReg(SrcReg, getKillRegState(KillSrc));
- else {
+ // if (Subtarget.hasZeroCycleRegMoveFPR128()) { need rebase
+ ++NumZeroCycleRegMoveFPR128;
+ // }
+ } else {
BuildMI(MBB, I, DL, get(AArch64::STRQpre))
.addReg(AArch64::SP, RegState::Define)
.addReg(SrcReg, getKillRegState(KillSrc))
@@ -5307,6 +5338,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
AArch64::FPR64RegClass.contains(SrcReg)) {
BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
+ if (Subtarget.hasZeroCycleRegMoveFPR64()) {
+ ++NumZeroCycleRegMoveFPR64;
+ }
return;
}
@@ -5326,9 +5360,13 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestRegD)
.addReg(SrcRegD, RegState::Undef)
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
+ ++NumZeroCycleRegMoveFPR64;
} else {
BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
+ if (Subtarget.hasZeroCycleRegMoveFPR32()) {
+ ++NumZeroCycleRegMoveFPR32;
+ }
}
return;
}
@@ -5349,6 +5387,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestRegD)
.addReg(SrcRegD, RegState::Undef)
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
+ ++NumZeroCycleRegMoveFPR64;
} else {
DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
&AArch64::FPR32RegClass);
@@ -5356,6 +5395,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
&AArch64::FPR32RegClass);
BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
+ if (Subtarget.hasZeroCycleRegMoveFPR32()) {
+ ++NumZeroCycleRegMoveFPR32;
+ }
}
return;
}
@@ -5376,6 +5418,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestRegD)
.addReg(SrcRegD, RegState::Undef)
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
+ ++NumZeroCycleRegMoveFPR64;
} else {
DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
&AArch64::FPR32RegClass);
@@ -5383,6 +5426,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
&AArch64::FPR32RegClass);
BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
+ if (Subtarget.hasZeroCycleRegMoveFPR32()) {
+ ++NumZeroCycleRegMoveFPR32;
+ }
}
return;
}
More information about the llvm-commits
mailing list