[llvm] 5ba458c - MCFixup: Replace getTargetKind with getKind
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 15 00:21:12 PDT 2025
Author: Fangrui Song
Date: 2025-07-15T00:21:07-07:00
New Revision: 5ba458c559b04efca307dc86f8265cf6dffaf666
URL: https://github.com/llvm/llvm-project/commit/5ba458c559b04efca307dc86f8265cf6dffaf666
DIFF: https://github.com/llvm/llvm-project/commit/5ba458c559b04efca307dc86f8265cf6dffaf666.diff
LOG: MCFixup: Replace getTargetKind with getKind
Added:
Modified:
llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
index 830107cde39c7..b9d3e1bf835b4 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -417,7 +417,7 @@ static bool shouldForceRelocation(const MCFixup &Fixup) {
// same page as the ADRP and the instruction should encode 0x0. Assuming the
// section isn't 0x1000-aligned, we therefore need to delegate this decision
// to the linker -- a relocation!
- return Fixup.getTargetKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21;
+ return Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21;
}
void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
@@ -431,7 +431,7 @@ void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
if (mc::isRelocation(Kind))
return;
- if (Fixup.getTargetKind() == FK_Data_8 && TheTriple.isOSBinFormatELF()) {
+ if (Fixup.getKind() == FK_Data_8 && TheTriple.isOSBinFormatELF()) {
auto RefKind = static_cast<AArch64::Specifier>(Target.getSpecifier());
AArch64::Specifier SymLoc = AArch64::getSymbolLoc(RefKind);
if (SymLoc == AArch64::S_AUTH || SymLoc == AArch64::S_AUTHADDR) {
@@ -488,7 +488,7 @@ void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
AArch64::Specifier RefKind =
static_cast<AArch64::Specifier>(Target.getSpecifier());
if (AArch64::getSymbolLoc(RefKind) == AArch64::S_SABS ||
- (!RefKind && Fixup.getTargetKind() == AArch64::fixup_aarch64_movw)) {
+ (!RefKind && Fixup.getKind() == AArch64::fixup_aarch64_movw)) {
// If the immediate is negative, generate MOVN else MOVZ.
// (Bit 30 = 0) ==> MOVN, (Bit 30 = 1) ==> MOVZ.
if (SignedValue < 0)
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
index 7491fd19e4d64..7618a57691868 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
@@ -57,7 +57,7 @@ AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
// assumes IsILP32 is true
bool AArch64ELFObjectWriter::isNonILP32reloc(const MCFixup &Fixup,
AArch64::Specifier RefKind) const {
- if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
+ if (Fixup.getKind() != AArch64::fixup_aarch64_movw)
return false;
switch (RefKind) {
case AArch64::S_ABS_G3:
@@ -84,7 +84,7 @@ bool AArch64ELFObjectWriter::isNonILP32reloc(const MCFixup &Fixup,
unsigned AArch64ELFObjectWriter::getRelocType(const MCFixup &Fixup,
const MCValue &Target,
bool IsPCRel) const {
- unsigned Kind = Fixup.getTargetKind();
+ auto Kind = Fixup.getKind();
AArch64::Specifier RefKind =
static_cast<AArch64::Specifier>(Target.getSpecifier());
AArch64::Specifier SymLoc = AArch64::getSymbolLoc(RefKind);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
index 22ae5f4e71915..998ea1ffe32be 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -76,7 +76,7 @@ unsigned AMDGPUELFObjectWriter::getRelocType(const MCFixup &Fixup,
return IsPCRel ? ELF::R_AMDGPU_REL64 : ELF::R_AMDGPU_ABS64;
}
- if (Fixup.getTargetKind() == AMDGPU::fixup_si_sopp_br) {
+ if (Fixup.getKind() == AMDGPU::fixup_si_sopp_br) {
const auto *SymA = Target.getAddSym();
assert(SymA);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 31e6cc5e7e81b..164acdec4544b 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -316,7 +316,7 @@ bool ARMAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
uint64_t Value,
bool Resolved) const {
const MCSymbol *Sym = Target.getAddSym();
- if (needsInterworking(*Asm, Sym, Fixup.getTargetKind()))
+ if (needsInterworking(*Asm, Sym, Fixup.getKind()))
return true;
if (!Resolved)
@@ -947,7 +947,7 @@ bool ARMAsmBackend::shouldForceRelocation(const MCFixup &Fixup,
}
// Create relocations for unconditional branches to function symbols with
//
diff erent execution mode in ELF binaries.
- if (needsInterworking(*Asm, Sym, Fixup.getTargetKind()))
+ if (needsInterworking(*Asm, Sym, Fixup.getKind()))
return true;
// We must always generate a relocation for BL/BLX instructions if we have
// a symbol to reference, as the linker relies on knowing the destination
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
index b0f3289e284de..50e9ca1d3759d 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
@@ -75,7 +75,7 @@ bool ARMELFObjectWriter::needsRelocateWithSymbol(const MCValue &V,
unsigned ARMELFObjectWriter::getRelocType(const MCFixup &Fixup,
const MCValue &Target,
bool IsPCRel) const {
- unsigned Kind = Fixup.getTargetKind();
+ auto Kind = Fixup.getKind();
uint8_t Specifier = Target.getSpecifier();
auto CheckFDPIC = [&](uint32_t Type) {
if (getOSABI() != ELF::ELFOSABI_ARM_FDPIC)
diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
index 958790d49d087..dda87537809cf 100644
--- a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
+++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
@@ -90,7 +90,7 @@ void BPFAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
Data[Fixup.getOffset() + 1] = 0x1;
support::endian::write32be(&Data[Fixup.getOffset() + 4], Value);
}
- } else if (Fixup.getTargetKind() == BPF::FK_BPF_PCRel_4) {
+ } else if (Fixup.getKind() == BPF::FK_BPF_PCRel_4) {
// The input Value represents the number of bytes.
Value = (uint32_t)((Value - 8) / 8);
support::endian::write<uint32_t>(&Data[Fixup.getOffset() + 4], Value,
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
index 1de82e6cc6ce8..d042d26e6ef21 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
@@ -39,7 +39,7 @@ unsigned CSKYELFObjectWriter::getRelocType(const MCFixup &Fixup,
bool IsPCRel) const {
const MCExpr *Expr = Fixup.getValue();
// Determine the type of the relocation
- unsigned Kind = Fixup.getTargetKind();
+ auto Kind = Fixup.getKind();
uint8_t Modifier = Target.getSpecifier();
switch (Target.getSpecifier()) {
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
index af108e9ee7655..3dbf7683cdade 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
@@ -157,7 +157,7 @@ void LoongArchAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
MCContext &Ctx = getContext();
// Fixup leb128 separately.
- if (Fixup.getTargetKind() == FK_Data_leb128)
+ if (Fixup.getKind() == FK_Data_leb128)
return fixupLeb128(Ctx, Fixup, Data, Value);
// Apply any target-specific value adjustments.
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
index faf3cba59a53c..fb741afa77e57 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
@@ -68,7 +68,7 @@ unsigned LoongArchELFObjectWriter::getRelocType(const MCFixup &Fixup,
break;
}
- unsigned Kind = Fixup.getTargetKind();
+ auto Kind = Fixup.getKind();
if (mc::isRelocation(Fixup.getKind()))
return Kind;
switch (Kind) {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
index 25e31941bbb45..ad8f5f0a09745 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
@@ -156,7 +156,7 @@ unsigned MipsELFObjectWriter::getRelocType(const MCFixup &Fixup,
const MCValue &Target,
bool IsPCRel) const {
// Determine the type of the relocation.
- unsigned Kind = Fixup.getTargetKind();
+ auto Kind = Fixup.getKind();
switch (Target.getSpecifier()) {
case Mips::S_DTPREL:
case Mips::S_DTPREL_HI:
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
index 66daece94f747..a5d3be40c5cfc 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
@@ -174,7 +174,8 @@ unsigned PPCELFObjectWriter::getRelocType(const MCFixup &Fixup,
}
} else {
switch (Fixup.getKind()) {
- default: llvm_unreachable("invalid fixup kind!");
+ default:
+ llvm_unreachable("invalid fixup kind!");
case PPC::fixup_ppc_br24abs:
Type = ELF::R_PPC_ADDR24;
break;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 7c6379cf758b8..e42d6c539a349 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -109,7 +109,7 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
uint64_t Value,
bool Resolved) const {
int64_t Offset = int64_t(Value);
- unsigned Kind = Fixup.getTargetKind();
+ auto Kind = Fixup.getKind();
// Return true if the symbol is unresolved.
if (!Resolved)
@@ -678,7 +678,7 @@ static const MCFixup *getPCRelHiFixup(const MCSpecifierExpr &Expr,
for (const MCFixup &F : DF->getFixups()) {
if (F.getOffset() != Offset)
continue;
- auto Kind = F.getTargetKind();
+ auto Kind = F.getKind();
if (!mc::isRelocation(F.getKind())) {
if (Kind == RISCV::fixup_riscv_pcrel_hi20) {
*DFOut = DF;
@@ -745,7 +745,7 @@ std::optional<bool> RISCVAsmBackend::evaluateFixup(const MCFragment &,
Value = Asm->getSymbolOffset(SA) + AUIPCTarget.getConstant();
Value -= Asm->getFragmentOffset(*AUIPCDF) + AUIPCFixup->getOffset();
- return AUIPCFixup->getTargetKind() == RISCV::fixup_riscv_pcrel_hi20 &&
+ return AUIPCFixup->getKind() == RISCV::fixup_riscv_pcrel_hi20 &&
isPCRelFixupResolved(AUIPCTarget.getAddSym(), *AUIPCDF);
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
index 146e3ab2fc38d..9bf7896e1f1e2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
@@ -48,7 +48,7 @@ RISCVELFObjectWriter::~RISCVELFObjectWriter() = default;
unsigned RISCVELFObjectWriter::getRelocType(const MCFixup &Fixup,
const MCValue &Target,
bool IsPCRel) const {
- unsigned Kind = Fixup.getTargetKind();
+ auto Kind = Fixup.getKind();
auto Spec = Target.getSpecifier();
switch (Spec) {
case ELF::R_RISCV_TPREL_HI20:
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
index 2a5c4b6712ef5..4a9c88bfa6d39 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
@@ -68,7 +68,7 @@ unsigned SparcELFObjectWriter::getRelocType(const MCFixup &Fixup,
// Extract the relocation type from the fixup kind, after applying STT_TLS as
// needed.
- unsigned Kind = Fixup.getTargetKind();
+ auto Kind = Fixup.getKind();
if (mc::isRelocation(Fixup.getKind()))
return Kind;
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
index c34425f6661b4..0dabd98a38f44 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
@@ -258,7 +258,7 @@ void X86MachObjectWriter::RecordX86_64Relocation(
// x86_64 distinguishes movq foo at GOTPCREL so that the linker can
// rewrite the movq to an leaq at link time if the symbol ends up in
// the same linkage unit.
- if (Fixup.getTargetKind() == X86::reloc_riprel_4byte_movq_load)
+ if (Fixup.getKind() == X86::reloc_riprel_4byte_movq_load)
Type = MachO::X86_64_RELOC_GOT_LOAD;
else
Type = MachO::X86_64_RELOC_GOT;
@@ -320,7 +320,7 @@ void X86MachObjectWriter::RecordX86_64Relocation(
return;
} else {
Type = MachO::X86_64_RELOC_UNSIGNED;
- if (Fixup.getTargetKind() == X86::reloc_signed_4byte) {
+ if (Fixup.getKind() == X86::reloc_signed_4byte) {
reportError(
Fixup.getLoc(),
"32-bit absolute addressing is not supported in 64-bit mode");
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