[llvm] dae72bc - [X86] freeze-unary.ll - show tests failing to remove freeze from ISD::ABS node
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 15 00:10:37 PDT 2025
Author: Simon Pilgrim
Date: 2025-07-15T08:09:30+01:00
New Revision: dae72bc659d79f59e3b26a948158e3f37b33471b
URL: https://github.com/llvm/llvm-project/commit/dae72bc659d79f59e3b26a948158e3f37b33471b
DIFF: https://github.com/llvm/llvm-project/commit/dae72bc659d79f59e3b26a948158e3f37b33471b.diff
LOG: [X86] freeze-unary.ll - show tests failing to remove freeze from ISD::ABS node
Unlike the abs intrinsic, the ISD::ABS node defines ABS(INT_MIN) -> INT_MIN, not poison is generated
Added:
Modified:
llvm/test/CodeGen/X86/freeze-unary.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/freeze-unary.ll b/llvm/test/CodeGen/X86/freeze-unary.ll
index 8602c385af834..2cbcd0e04e100 100644
--- a/llvm/test/CodeGen/X86/freeze-unary.ll
+++ b/llvm/test/CodeGen/X86/freeze-unary.ll
@@ -70,6 +70,108 @@ define <2 x i64> @freeze_zext_vec(<2 x i16> %a0) nounwind {
ret <2 x i64> %z
}
+define i32 @freeze_abs(i32 %a0) nounwind {
+; X86-LABEL: freeze_abs:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: negl %ecx
+; X86-NEXT: cmovsl %eax, %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: cmovsl %ecx, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_abs:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: negl %ecx
+; X64-NEXT: cmovsl %edi, %ecx
+; X64-NEXT: movl %ecx, %eax
+; X64-NEXT: negl %eax
+; X64-NEXT: cmovsl %ecx, %eax
+; X64-NEXT: retq
+ %x = call i32 @llvm.abs.i32(i32 %a0, i1 0)
+ %f = freeze i32 %x
+ %r = call i32 @llvm.abs.i32(i32 %f, i1 0)
+ ret i32 %r
+}
+
+define <4 x i32> @freeze_abs_vec(<4 x i32> %a0) nounwind {
+; X86-LABEL: freeze_abs_vec:
+; X86: # %bb.0:
+; X86-NEXT: movdqa %xmm0, %xmm1
+; X86-NEXT: psrad $31, %xmm1
+; X86-NEXT: pxor %xmm1, %xmm0
+; X86-NEXT: psubd %xmm1, %xmm0
+; X86-NEXT: movdqa %xmm0, %xmm1
+; X86-NEXT: psrad $31, %xmm1
+; X86-NEXT: pxor %xmm1, %xmm0
+; X86-NEXT: psubd %xmm1, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_abs_vec:
+; X64: # %bb.0:
+; X64-NEXT: pabsd %xmm0, %xmm0
+; X64-NEXT: pabsd %xmm0, %xmm0
+; X64-NEXT: retq
+ %x = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a0, i1 0)
+ %f = freeze <4 x i32> %x
+ %r = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %f, i1 0)
+ ret <4 x i32> %r
+}
+
+define i32 @freeze_abs_undef(i32 %a0) nounwind {
+; X86-LABEL: freeze_abs_undef:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: negl %ecx
+; X86-NEXT: cmovsl %eax, %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: cmovsl %ecx, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_abs_undef:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: negl %ecx
+; X64-NEXT: cmovsl %edi, %ecx
+; X64-NEXT: movl %ecx, %eax
+; X64-NEXT: negl %eax
+; X64-NEXT: cmovsl %ecx, %eax
+; X64-NEXT: retq
+ %x = call i32 @llvm.abs.i32(i32 %a0, i1 -1)
+ %f = freeze i32 %x
+ %r = call i32 @llvm.abs.i32(i32 %f, i1 -1)
+ ret i32 %r
+}
+
+define <4 x i32> @freeze_abs_undef_vec(<4 x i32> %a0) nounwind {
+; X86-LABEL: freeze_abs_undef_vec:
+; X86: # %bb.0:
+; X86-NEXT: movdqa %xmm0, %xmm1
+; X86-NEXT: psrad $31, %xmm1
+; X86-NEXT: pxor %xmm1, %xmm0
+; X86-NEXT: psubd %xmm1, %xmm0
+; X86-NEXT: movdqa %xmm0, %xmm1
+; X86-NEXT: psrad $31, %xmm1
+; X86-NEXT: pxor %xmm1, %xmm0
+; X86-NEXT: psubd %xmm1, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_abs_undef_vec:
+; X64: # %bb.0:
+; X64-NEXT: pabsd %xmm0, %xmm0
+; X64-NEXT: pabsd %xmm0, %xmm0
+; X64-NEXT: retq
+ %x = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a0, i1 -1)
+ %f = freeze <4 x i32> %x
+ %r = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %f, i1 -1)
+ ret <4 x i32> %r
+}
+
define i32 @freeze_bswap(i32 %a0) nounwind {
; X86-LABEL: freeze_bswap:
; X86: # %bb.0:
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