[llvm] 0b674f4 - MCFixup: Replace getTargetKind with getKind
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 15 00:08:50 PDT 2025
Author: Fangrui Song
Date: 2025-07-15T00:08:45-07:00
New Revision: 0b674f4c52237fed91c142ca3766b58f335fe120
URL: https://github.com/llvm/llvm-project/commit/0b674f4c52237fed91c142ca3766b58f335fe120
DIFF: https://github.com/llvm/llvm-project/commit/0b674f4c52237fed91c142ca3766b58f335fe120.diff
LOG: MCFixup: Replace getTargetKind with getKind
MCFixupKind is now a type alias (fixup kinds are inherently
target-specific). getTargetKind is no longer necessary.
Added:
Modified:
llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
index 84884d98e6f9c..830107cde39c7 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -142,7 +142,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
uint64_t Value, MCContext &Ctx,
const Triple &TheTriple, bool IsResolved) {
int64_t SignedValue = static_cast<int64_t>(Value);
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
llvm_unreachable("Unknown fixup kind!");
case AArch64::fixup_aarch64_pcrel_adr_imm21:
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
index c3881fc79ba62..7491fd19e4d64 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
@@ -212,7 +212,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(const MCFixup &Fixup,
} else {
if (IsILP32 && isNonILP32reloc(Fixup, RefKind))
return ELF::R_AARCH64_NONE;
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case FK_Data_1:
reportError(Fixup.getLoc(), "1-byte data relocations not supported");
return ELF::R_AARCH64_NONE;
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
index 61458d7c24be0..1ac340a1b58a2 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
@@ -53,7 +53,7 @@ bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
RelocType = unsigned(MachO::ARM64_RELOC_UNSIGNED);
Log2Size = ~0U;
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
return false;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
index e7d0e1838fa63..2a920f6feb1c9 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -108,7 +108,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
MCContext *Ctx) {
int64_t SignedValue = static_cast<int64_t>(Value);
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case AMDGPU::fixup_si_sopp_br: {
int64_t BrImm = (SignedValue - 4) / 4;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 376bddb120d5f..31e6cc5e7e81b 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -215,7 +215,7 @@ static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
uint64_t Value) const {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case ARM::fixup_arm_thumb_br: {
// Relaxing tB to t2B. tB has a signed 12-bit displacement with the
// low bit being an implied zero. There's an implied +4 offset for the
@@ -1093,7 +1093,7 @@ std::optional<bool> ARMAsmBackend::evaluateFixup(const MCFragment &F,
// For a few PC-relative fixups in Thumb mode, offsets need to be aligned
// down. We compensate here because the default handler's `Value` decrement
// doesn't account for this alignment.
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case ARM::fixup_t2_ldst_pcrel_12:
case ARM::fixup_t2_pcrel_10:
case ARM::fixup_t2_pcrel_9:
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
index b0ebb74424c78..b0f3289e284de 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
@@ -105,7 +105,7 @@ unsigned ARMELFObjectWriter::getRelocType(const MCFixup &Fixup,
}
if (IsPCRel) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
reportError(Fixup.getLoc(), "unsupported relocation type");
return ELF::R_ARM_NONE;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
index c0c40ade5810a..354de8fd7b4bb 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
@@ -192,7 +192,7 @@ void ARMMachObjectWriter::recordARMScatteredHalfRelocation(
// relocation entry in the low 16 bits of r_address field.
unsigned ThumbBit = 0;
unsigned MovtBit = 0;
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default: break;
case ARM::fixup_arm_movt_hi16:
MovtBit = 1;
@@ -465,7 +465,7 @@ void ARMMachObjectWriter::recordRelocation(MachObjectWriter *Writer,
// PAIR. I.e. it's correct that we insert the high bits of the addend in the
// MOVW case here. relocation entries.
uint32_t Value = 0;
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default: break;
case ARM::fixup_arm_movw_lo16:
case ARM::fixup_t2_movw_lo16:
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
index ce1da6e58b9cd..062b4356420ab 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
@@ -71,7 +71,7 @@ MCFixupKindInfo CSKYAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
MCContext &Ctx) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
llvm_unreachable("Unknown fixup kind!");
case CSKY::fixup_csky_got32:
@@ -166,7 +166,7 @@ bool CSKYAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
return true;
int64_t Offset = int64_t(Value);
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
return false;
case CSKY::fixup_csky_pcrel_imm10_scale2:
@@ -186,7 +186,7 @@ std::optional<bool> CSKYAsmBackend::evaluateFixup(const MCFragment &F,
// For a few PC-relative fixups, offsets need to be aligned down. We
// compensate here because the default handler's `Value` decrement doesn't
// account for this alignment.
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case CSKY::fixup_csky_pcrel_uimm16_scale4:
case CSKY::fixup_csky_pcrel_uimm8_scale4:
case CSKY::fixup_csky_pcrel_uimm7_scale4:
@@ -264,7 +264,7 @@ bool CSKYAsmBackend::shouldForceRelocation(const MCFixup &Fixup,
const MCValue &Target /*STI*/) {
if (Target.getSpecifier())
return true;
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
break;
case CSKY::fixup_csky_doffset_imm18:
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index de7bd5d4b2c66..287bdc5bfd4d4 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -200,7 +200,7 @@ class HexagonAsmBackend : public MCAsmBackend {
}
bool shouldForceRelocation(const MCFixup &Fixup) {
- switch(Fixup.getTargetKind()) {
+ switch(Fixup.getKind()) {
default:
llvm_unreachable("Unknown Fixup Kind!");
@@ -452,7 +452,7 @@ class HexagonAsmBackend : public MCAsmBackend {
return false;
// If we cannot resolve the fixup value, it requires relaxation.
if (!Resolved) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case fixup_Hexagon_B22_PCREL:
// GetFixupCount assumes B22 won't relax
[[fallthrough]];
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
index ed381c33225d2..9752f3a131205 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
@@ -56,7 +56,7 @@ unsigned HexagonELFObjectWriter::getRelocType(const MCFixup &Fixup,
default:
break;
}
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
report_fatal_error("Unrecognized relocation type");
break;
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
index 1b8893029bb33..af108e9ee7655 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
@@ -90,7 +90,7 @@ static void reportOutOfRangeError(MCContext &Ctx, SMLoc Loc, unsigned N) {
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
MCContext &Ctx) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
llvm_unreachable("Unknown fixup kind");
case FK_Data_1:
@@ -247,7 +247,7 @@ bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
bool LoongArchAsmBackend::shouldForceRelocation(const MCFixup &Fixup,
const MCValue &Target) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
return STI.hasFeature(LoongArch::FeatureRelax);
case FK_Data_1:
diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp
index 1fdc1f799fe52..117dd31e7f053 100644
--- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp
+++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp
@@ -30,7 +30,7 @@ class MSP430ELFObjectWriter : public MCELFObjectTargetWriter {
unsigned getRelocType(const MCFixup &Fixup, const MCValue &,
bool IsPCRel) const override {
// Translate fixup kind to ELF relocation type.
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case FK_Data_1: return ELF::R_MSP430_8;
case FK_Data_2: return ELF::R_MSP430_16_BYTE;
case FK_Data_4: return ELF::R_MSP430_32;
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
index 53312e36fb9da..66daece94f747 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
@@ -96,7 +96,7 @@ unsigned PPCELFObjectWriter::getRelocType(const MCFixup &Fixup,
// determine the type of the relocation
unsigned Type = 0;
if (IsPCRel) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
llvm_unreachable("Unimplemented");
case PPC::fixup_ppc_br24:
@@ -173,7 +173,7 @@ unsigned PPCELFObjectWriter::getRelocType(const MCFixup &Fixup,
break;
}
} else {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default: llvm_unreachable("invalid fixup kind!");
case PPC::fixup_ppc_br24abs:
Type = ELF::R_PPC_ADDR24;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 4c579e23e2410..7c6379cf758b8 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -474,7 +474,7 @@ bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
MCContext &Ctx) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
llvm_unreachable("Unknown fixup kind!");
case FK_Data_1:
@@ -706,7 +706,7 @@ std::optional<bool> RISCVAsmBackend::evaluateFixup(const MCFragment &,
const MCFixup *AUIPCFixup;
const MCFragment *AUIPCDF;
MCValue AUIPCTarget;
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
// Use default handling for `Value` and `IsResolved`.
return {};
@@ -752,7 +752,7 @@ std::optional<bool> RISCVAsmBackend::evaluateFixup(const MCFragment &,
void RISCVAsmBackend::maybeAddVendorReloc(const MCFragment &F,
const MCFixup &Fixup) {
StringRef VendorIdentifier;
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
// No Vendor Relocation Required.
return;
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
index 2a581d381d4ab..2a5c4b6712ef5 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
@@ -93,7 +93,7 @@ unsigned SparcELFObjectWriter::getRelocType(const MCFixup &Fixup,
}
// clang-format off
- switch(Fixup.getTargetKind()) {
+ switch(Fixup.getKind()) {
default:
llvm_unreachable("Unimplemented fixup -> relocation");
case FK_NONE: return ELF::R_SPARC_NONE;
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
index e09a916d48c90..f987621522477 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
@@ -154,7 +154,7 @@ class ELFVEAsmBackend : public VEAsmBackend {
void VEAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
uint64_t Value, bool IsResolved) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case VE::fixup_ve_tls_gd_hi32:
case VE::fixup_ve_tls_gd_lo32:
case VE::fixup_ve_tpoff_hi32:
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
index 1597e7d080f03..41f31eb3b8199 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
@@ -56,7 +56,7 @@ unsigned VEELFObjectWriter::getRelocType(const MCFixup &Fixup,
}
if (IsPCRel) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
return ELF::R_VE_NONE;
@@ -84,7 +84,7 @@ unsigned VEELFObjectWriter::getRelocType(const MCFixup &Fixup,
}
}
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
default:
reportError(Fixup.getLoc(), "Unknown ELF relocation type");
return ELF::R_VE_NONE;
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index ff2df3d5b192a..54853e3f858e9 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -686,7 +686,7 @@ std::optional<bool> X86AsmBackend::evaluateFixup(const MCFragment &,
MCFixup &Fixup,
MCValue &Target, uint64_t &) {
if (Fixup.isPCRel()) {
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case FK_Data_1:
Target.setConstant(Target.getConstant() - 1);
break;
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
index 671f1d04daf23..9167794a51e8b 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
@@ -144,7 +144,7 @@ std::optional<bool> XtensaAsmBackend::evaluateFixup(const MCFragment &F,
// For a few PC-relative fixups, offsets need to be aligned down. We
// compensate here because the default handler's `Value` decrement doesn't
// account for this alignment.
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case Xtensa::fixup_xtensa_call_18:
case Xtensa::fixup_xtensa_l32r_16:
Value = (Asm->getFragmentOffset(F) + Fixup.getOffset()) % 4;
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