[llvm] [CostModel/RISCV] Fix costs of vector [l](lrint|lround) (PR #146058)

[Craig Topper via llvm-commits]

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@@ -1251,11 +1248,45 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   switch (ICA.getID()) {
   case Intrinsic::lrint:
   case Intrinsic::llrint:
-    // We can't currently lower half or bfloat vector lrint/llrint.
-    if (auto *VecTy = dyn_cast<VectorType>(ICA.getArgTypes()[0]);
-        VecTy && VecTy->getElementType()->is16bitFPTy())
-      return InstructionCost::getInvalid();
-    [[fallthrough]];
+  case Intrinsic::lround:
+  case Intrinsic::llround: {
+    auto LT = getTypeLegalizationCost(RetTy);
+    if (ST->hasVInstructions() && LT.second.isVector()) {
+      ArrayRef<unsigned> Ops;
+      unsigned DstEltSz =
+          DL.getTypeSizeInBits(cast<VectorType>(RetTy)->getElementType());
+      if (LT.second.getVectorElementType() == MVT::bf16) {
+        if (DstEltSz == 64 && ST->is64Bit())
+          // vfwcvtbf16.f.f.v v9, v8
+          // vfcvt.x.f.v v8, v9
+          Ops = {RISCV::VFWCVTBF16_F_F_V, RISCV::VFCVT_X_F_V};
+        else
+          // vfwcvtbf16.f.f.v v9, v8
+          // vfwcvt.x.f.v v8, v9
+          Ops = {RISCV::VFWCVTBF16_F_F_V, RISCV::VFWCVT_X_F_V};
+      } else if (LT.second.getVectorElementType() == MVT::f16 &&
+                 !ST->hasVInstructionsF16()) {
+        if (DstEltSz == 64 && ST->is64Bit())
+          // vfwcvt.f.f.v v9, v8
+          // vfwcvt.x.f.v v8, v9
+          Ops = {RISCV::VFWCVT_F_F_V, RISCV::VFWCVT_X_F_V};
+        else
+          // vfwcvt.f.f.v v9, v8
+          // vfcvt.x.f.v v8, v9
+          Ops = {RISCV::VFWCVT_F_F_V, RISCV::VFCVT_X_F_V};
+
+      } else if (DstEltSz == 32 && ST->is64Bit()) {
+        // vfncvt.x.f.w v10, v8
----------------
topperc wrote:

It would only be vfncvt if the source type was f64. The source type could be f32.

https://github.com/llvm/llvm-project/pull/146058