[llvm] [CostModel/RISCV] Fix costs of vector [l](lrint|lround) (PR #146058)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 10 10:31:41 PDT 2025


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@@ -1251,11 +1248,45 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   switch (ICA.getID()) {
   case Intrinsic::lrint:
   case Intrinsic::llrint:
-    // We can't currently lower half or bfloat vector lrint/llrint.
-    if (auto *VecTy = dyn_cast<VectorType>(ICA.getArgTypes()[0]);
-        VecTy && VecTy->getElementType()->is16bitFPTy())
-      return InstructionCost::getInvalid();
-    [[fallthrough]];
+  case Intrinsic::lround:
+  case Intrinsic::llround: {
+    auto LT = getTypeLegalizationCost(RetTy);
+    if (ST->hasVInstructions() && LT.second.isVector()) {
+      ArrayRef<unsigned> Ops;
+      unsigned DstEltSz =
+          DL.getTypeSizeInBits(cast<VectorType>(RetTy)->getElementType());
+      if (LT.second.getVectorElementType() == MVT::bf16) {
+        if (DstEltSz == 64 && ST->is64Bit())
----------------
topperc wrote:

Why is ST->is64Bit() relevant? That's the size of Xlen, but there's not scalar types involved here

https://github.com/llvm/llvm-project/pull/146058


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