[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (PR #146675)

[via llvm-commits]

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@@ -1461,6 +1485,31 @@ def : QCIMVCCIPat <SETLT,  QC_MVLTI>;
 def : QCIMVCCIPat <SETULT, QC_MVLTUI>;
 }
 
+let Predicates = [HasVendorXqcics, IsRV32] in {
+def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2),(XLenVT GPRNoX0:$rs3)),
+          (QC_SELECTEQI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs3, GPRNoX0:$rs2)>;
+
+let AddedComplexity = 1 in {
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hchandel wrote:

I tried this locally, but it disables xqcicm patterns when I give both `experimental-xqcicm` and `experimental-xqcics` even in cases when they should be used and in future, I think such scenarios are possible, where we enable both these extensions together. 

https://github.com/llvm/llvm-project/pull/146675