[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (PR #146675)
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Thu Jul 10 00:37:27 PDT 2025
https://github.com/hchandel updated https://github.com/llvm/llvm-project/pull/146675
>From 57fd83e2f43b48b7a146028c6c7f07cf5bf3987c Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Fri, 27 Jun 2025 17:30:21 +0530
Subject: [PATCH 1/7] [RISCV] Add ISel patterns for Qualcomm uC Xqcics
Add CodeGen support for conditional select instructions in this extension
Change-Id: I93b8e1210588d66237af7e709b4b6ea15fd837e2
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 30 ++++
llvm/test/CodeGen/RISCV/xqcics.ll | 173 ++++++++++++++++++++
3 files changed, 204 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/RISCV/xqcics.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c1212a8b1cf17..fb7d609f4b575 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -437,7 +437,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
if (!Subtarget.useCCMovInsn() && !Subtarget.hasVendorXTHeadCondMov() &&
- !Subtarget.hasVendorXqcicm())
+ !Subtarget.hasVendorXqcicm() && !Subtarget.hasVendorXqcics())
setOperationAction(ISD::SELECT, XLenVT, Custom);
if (Subtarget.hasVendorXqcia() && !Subtarget.is64Bit()) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index e8dd164714875..bbfb746b8398a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1312,6 +1312,22 @@ class QCIMVCCIPat<CondCode Cond, QCIMVCCI Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), simm5:$imm, Cond)), (XLenVT GPRNoX0:$rs3), (XLenVT GPRNoX0:$rd)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$imm, GPRNoX0:$rs3)>;
+class QCISELECTCCIPat<CondCode Cond, QCISELECTCCI Inst>
+ : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), simm5:$imm, Cond)), (XLenVT GPRNoX0:$rs2), (XLenVT GPRNoX0:$rs3)),
+ (Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, GPRNoX0:$rs3)>;
+
+class QCISELECTICCIPat<CondCode Cond, QCISELECTICCI Inst>
+ : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), simm5:$imm, Cond)), (XLenVT GPRNoX0:$rs2), simm5:$simm2),
+ (Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
+
+class QCISELECTICCPat<CondCode Cond, QCISELECTICC Inst>
+ : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs1), Cond)), (XLenVT GPRNoX0:$rs2), simm5:$simm2),
+ (Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
+
+class QCISELECTIICCPat<CondCode Cond, QCISELECTIICC Inst>
+ : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs1), Cond)), simm5:$simm1, simm5:$simm2),
+ (Inst GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2)>;
+
// Match `riscv_brcc` and lower to the appropriate XQCIBI branch instruction.
class BcciPat<CondCode Cond, QCIBranchInst_rii Inst, DAGOperand InTyImm>
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
@@ -1461,6 +1477,20 @@ def : QCIMVCCIPat <SETLT, QC_MVLTI>;
def : QCIMVCCIPat <SETULT, QC_MVLTUI>;
}
+let Predicates = [HasVendorXqcics, IsRV32] in {
+def : QCISELECTCCIPat <SETEQ, QC_SELECTEQI>;
+def : QCISELECTCCIPat <SETNE, QC_SELECTNEI>;
+
+def : QCISELECTICCIPat <SETEQ, QC_SELECTIEQI>;
+def : QCISELECTICCIPat <SETNE, QC_SELECTINEI>;
+
+def : QCISELECTICCPat <SETEQ, QC_SELECTIEQ>;
+def : QCISELECTICCPat <SETNE, QC_SELECTINE>;
+
+def : QCISELECTIICCPat <SETEQ, QC_SELECTIIEQ>;
+def : QCISELECTIICCPat <SETNE, QC_SELECTIINE>;
+} // Predicates = [HasVendorXqcics, IsRV32]
+
//===----------------------------------------------------------------------===/i
// Compress Instruction tablegen backend.
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
new file mode 100644
index 0000000000000..731632575d542
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -0,0 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test that we are able to generate the Xqcics instructions
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32I
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
+
+define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: beq a0, a1, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eq:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %a, 11
+ %sel = select i1 %cmp, i32 %x, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ne:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: bne a0, a1, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: .LBB1_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_ne:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 %a, 11
+ %sel = select i1 %cmp, i32 %x, i32 %y
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eqi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: beq a0, a1, .LBB2_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB2_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eqi:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %sel = select i1 %cmp, i32 %x, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_nei:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bne a0, a1, .LBB3_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB3_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_nei:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 %a, %b
+ %sel = select i1 %cmp, i32 %x, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ieqi:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 12
+; RV32I-NEXT: beq a0, a1, .LBB4_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB4_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_ieqi:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %a, 12
+ %sel = select i1 %cmp, i32 %x, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_inei:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 12
+; RV32I-NEXT: bne a0, a1, .LBB5_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_inei:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 %a, 12
+ %sel = select i1 %cmp, i32 %x, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_eqii(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eqii:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: beq a0, a1, .LBB6_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a0, 11
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB6_2:
+; RV32I-NEXT: li a0, 13
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eqii:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectiieq a0, a1, 13, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %sel = select i1 %cmp, i32 13, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_neii(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_neii:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bne a0, a1, .LBB7_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a0, 11
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB7_2:
+; RV32I-NEXT: li a0, 13
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_neii:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectiine a0, a1, 13, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 %a, %b
+ %sel = select i1 %cmp, i32 13, i32 11
+ ret i32 %sel
+}
+
>From 0c4644f9c3137bc9d7182d5dfd154ba8a6dd2c3a Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Mon, 30 Jun 2025 16:29:08 +0530
Subject: [PATCH 2/7] fixup! Add some more patterns and tests
Change-Id: Ifb18259f2ef860e05b4f673aceebf349d7ff8103
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 14 ++
llvm/test/CodeGen/RISCV/xqcics.ll | 236 ++++++++++++++++++--
2 files changed, 236 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index bbfb746b8398a..bc10827fcfee1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1320,10 +1320,18 @@ class QCISELECTICCIPat<CondCode Cond, QCISELECTICCI Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), simm5:$imm, Cond)), (XLenVT GPRNoX0:$rs2), simm5:$simm2),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
+class QCISELECTICCIPatInv<CondCode Cond, QCISELECTICCI Inst>
+ : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), simm5:$imm, Cond)), simm5:$simm2, (XLenVT GPRNoX0:$rs2)),
+ (Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
+
class QCISELECTICCPat<CondCode Cond, QCISELECTICC Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs1), Cond)), (XLenVT GPRNoX0:$rs2), simm5:$simm2),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
+class QCISELECTICCPatInv<CondCode Cond, QCISELECTICC Inst>
+ : Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs1), Cond)), simm5:$simm2, (XLenVT GPRNoX0:$rs2)),
+ (Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
+
class QCISELECTIICCPat<CondCode Cond, QCISELECTIICC Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs1), Cond)), simm5:$simm1, simm5:$simm2),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2)>;
@@ -1484,9 +1492,15 @@ def : QCISELECTCCIPat <SETNE, QC_SELECTNEI>;
def : QCISELECTICCIPat <SETEQ, QC_SELECTIEQI>;
def : QCISELECTICCIPat <SETNE, QC_SELECTINEI>;
+def : QCISELECTICCIPatInv <SETEQ, QC_SELECTINEI>;
+def : QCISELECTICCIPatInv <SETNE, QC_SELECTIEQI>;
+
def : QCISELECTICCPat <SETEQ, QC_SELECTIEQ>;
def : QCISELECTICCPat <SETNE, QC_SELECTINE>;
+def : QCISELECTICCPatInv <SETEQ, QC_SELECTINE>;
+def : QCISELECTICCPatInv <SETNE, QC_SELECTIEQ>;
+
def : QCISELECTIICCPat <SETEQ, QC_SELECTIIEQ>;
def : QCISELECTIICCPat <SETNE, QC_SELECTIINE>;
} // Predicates = [HasVendorXqcics, IsRV32]
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index 731632575d542..c0c07a9329179 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -26,14 +26,35 @@ entry:
ret i32 %sel
}
+define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq_c:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: beq a0, a1, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: .LBB1_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eq_c:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 11, %a
+ %sel = select i1 %cmp, i32 %x, i32 %y
+ ret i32 %sel
+}
+
define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ne:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
-; RV32I-NEXT: bne a0, a1, .LBB1_2
+; RV32I-NEXT: bne a0, a1, .LBB2_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: .LBB1_2: # %entry
+; RV32I-NEXT: .LBB2_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -47,13 +68,34 @@ entry:
ret i32 %sel
}
+define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ne_c:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 11
+; RV32I-NEXT: bne a0, a1, .LBB3_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: .LBB3_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_ne_c:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 11, %a
+ %sel = select i1 %cmp, i32 %x, i32 %y
+ ret i32 %sel
+}
+
define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eqi:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: beq a0, a1, .LBB2_2
+; RV32I-NEXT: beq a0, a1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB2_2: # %entry
+; RV32I-NEXT: .LBB4_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -67,13 +109,33 @@ entry:
ret i32 %sel
}
+define i32 @select_cc_example_eqi_c(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eqi_c:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: bne a0, a1, .LBB5_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eqi_c:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %a, %b
+ %sel = select i1 %cmp, i32 11, i32 %x
+ ret i32 %sel
+}
+
define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_nei:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: bne a0, a1, .LBB3_2
+; RV32I-NEXT: bne a0, a1, .LBB6_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB3_2: # %entry
+; RV32I-NEXT: .LBB6_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -87,14 +149,34 @@ entry:
ret i32 %sel
}
+define i32 @select_cc_example_nei_c(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_nei_c:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: beq a0, a1, .LBB7_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_nei_c:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 %a, %b
+ %sel = select i1 %cmp, i32 11, i32 %x
+ ret i32 %sel
+}
+
define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: beq a0, a1, .LBB4_2
+; RV32I-NEXT: beq a0, a1, .LBB8_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB4_2: # %entry
+; RV32I-NEXT: .LBB8_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -108,14 +190,77 @@ entry:
ret i32 %sel
}
+define i32 @select_cc_example_ieqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ieqi_c1:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 12
+; RV32I-NEXT: beq a0, a1, .LBB9_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_ieqi_c1:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 12, %a
+ %sel = select i1 %cmp, i32 %x, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ieqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ieqi_c2:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 12
+; RV32I-NEXT: bne a0, a1, .LBB10_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_ieqi_c2:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 %a, 12
+ %sel = select i1 %cmp, i32 11, i32 %x
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_ieqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_ieqi_c3:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 12
+; RV32I-NEXT: bne a0, a1, .LBB11_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_ieqi_c3:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp eq i32 12, %a
+ %sel = select i1 %cmp, i32 11, i32 %x
+ ret i32 %sel
+}
+
define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: bne a0, a1, .LBB5_2
+; RV32I-NEXT: bne a0, a1, .LBB12_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: .LBB12_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -129,14 +274,77 @@ entry:
ret i32 %sel
}
+define i32 @select_cc_example_inei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_inei_c1:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 12
+; RV32I-NEXT: bne a0, a1, .LBB13_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_inei_c1:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 12, %a
+ %sel = select i1 %cmp, i32 %x, i32 11
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_inei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_inei_c2:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 12
+; RV32I-NEXT: beq a0, a1, .LBB14_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_inei_c2:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 %a, 12
+ %sel = select i1 %cmp, i32 11, i32 %x
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_inei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_inei_c3:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 12
+; RV32I-NEXT: beq a0, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a2, 11
+; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_inei_c3:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cmp = icmp ne i32 12, %a
+ %sel = select i1 %cmp, i32 11, i32 %x
+ ret i32 %sel
+}
+
define i32 @select_cc_example_eqii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eqii:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: beq a0, a1, .LBB6_2
+; RV32I-NEXT: beq a0, a1, .LBB16_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 11
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB6_2:
+; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: li a0, 13
; RV32I-NEXT: ret
;
@@ -153,11 +361,11 @@ entry:
define i32 @select_cc_example_neii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_neii:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: bne a0, a1, .LBB7_2
+; RV32I-NEXT: bne a0, a1, .LBB17_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 11
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB7_2:
+; RV32I-NEXT: .LBB17_2:
; RV32I-NEXT: li a0, 13
; RV32I-NEXT: ret
;
>From d9db180bfdfbc6183ec75d4158ef74c407d07f0b Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Tue, 1 Jul 2025 12:37:35 +0530
Subject: [PATCH 3/7] fixup! AddedComplexity
Change-Id: I7e1a682ed0b2e20330c6985eb1bd9ac024e9987d
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index bc10827fcfee1..01d0cab04a21f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1486,8 +1486,10 @@ def : QCIMVCCIPat <SETULT, QC_MVLTUI>;
}
let Predicates = [HasVendorXqcics, IsRV32] in {
+let AddedComplexity = 1 in {
def : QCISELECTCCIPat <SETEQ, QC_SELECTEQI>;
def : QCISELECTCCIPat <SETNE, QC_SELECTNEI>;
+}
def : QCISELECTICCIPat <SETEQ, QC_SELECTIEQI>;
def : QCISELECTICCIPat <SETNE, QC_SELECTINEI>;
>From f3886c5c663fc52ce56ab6645443f026748b7f56 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Wed, 2 Jul 2025 12:46:39 +0530
Subject: [PATCH 4/7] fixup! Add one more pattern
Change-Id: I87527638542a2a7c89b9e782fa825bb398f3e082
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 3 +
llvm/test/CodeGen/RISCV/select-cond.ll | 209 ++++++++++++++++++++
2 files changed, 212 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 01d0cab04a21f..3d582c38d8277 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1486,6 +1486,9 @@ def : QCIMVCCIPat <SETULT, QC_MVLTUI>;
}
let Predicates = [HasVendorXqcics, IsRV32] in {
+def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2),(XLenVT GPRNoX0:$rs3)),
+ (QC_SELECTEQI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs3, GPRNoX0:$rs2)>;
+
let AddedComplexity = 1 in {
def : QCISELECTCCIPat <SETEQ, QC_SELECTEQI>;
def : QCISELECTCCIPat <SETNE, QC_SELECTNEI>;
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index d9f9ad379ee95..7ece32681baf9 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -5,6 +5,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32-THEAD
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32-XQCICM
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32-XQCICS
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
@@ -35,6 +37,12 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32-XQCICM-NEXT: mv a0, a1
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_trunc:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: andi a0, a0, 1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a1
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_trunc:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -80,6 +88,12 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32-XQCICM-NEXT: mv a0, a1
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_param:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: andi a0, a0, 1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a1
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_param:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -122,6 +136,13 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_eq:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: xor a0, a0, a1
+; RV32-XQCICS-NEXT: seqz a0, a0
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_eq:
; RV64: # %bb.0:
; RV64-NEXT: beq a0, a1, .LBB2_2
@@ -164,6 +185,13 @@ define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_ne:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: xor a0, a0, a1
+; RV32-XQCICS-NEXT: snez a0, a0
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_ne:
; RV64: # %bb.0:
; RV64-NEXT: bne a0, a1, .LBB3_2
@@ -206,6 +234,12 @@ define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_ugt:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a1, a0
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_ugt:
; RV64: # %bb.0:
; RV64-NEXT: bltu a1, a0, .LBB4_2
@@ -248,6 +282,12 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_uge:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a3
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_uge:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a0, a1, .LBB5_2
@@ -290,6 +330,12 @@ define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_ult:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_ult:
; RV64: # %bb.0:
; RV64-NEXT: bltu a0, a1, .LBB6_2
@@ -332,6 +378,12 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_ule:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a1, a0
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a3
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_ule:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a1, a0, .LBB7_2
@@ -374,6 +426,12 @@ define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_sgt:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: slt a0, a1, a0
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_sgt:
; RV64: # %bb.0:
; RV64-NEXT: blt a1, a0, .LBB8_2
@@ -416,6 +474,12 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_sge:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: slt a0, a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a3
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_sge:
; RV64: # %bb.0:
; RV64-NEXT: bge a0, a1, .LBB9_2
@@ -458,6 +522,12 @@ define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_slt:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: slt a0, a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_slt:
; RV64: # %bb.0:
; RV64-NEXT: blt a0, a1, .LBB10_2
@@ -500,6 +570,12 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i32_sle:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: slt a0, a1, a0
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a3
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i32_sle:
; RV64: # %bb.0:
; RV64-NEXT: bge a1, a0, .LBB11_2
@@ -550,6 +626,14 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_trunc:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: andi a1, a0, 1
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a3
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a2
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_trunc:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -601,6 +685,15 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a2
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_param:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: andi a5, a0, 1
+; RV32-XQCICS-NEXT: mv a0, a5
+; RV32-XQCICS-NEXT: qc.selecteqi a5, 0, a4, a2
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a1
+; RV32-XQCICS-NEXT: mv a1, a5
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_param:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@@ -657,6 +750,16 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_eq:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: xor a0, a0, a2
+; RV32-XQCICS-NEXT: or a1, a0, a1
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_eq:
; RV64: # %bb.0:
; RV64-NEXT: beq a0, a1, .LBB14_2
@@ -713,6 +816,16 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_ne:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: xor a0, a0, a2
+; RV32-XQCICS-NEXT: or a1, a0, a1
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_ne:
; RV64: # %bb.0:
; RV64-NEXT: bne a0, a1, .LBB15_2
@@ -774,6 +887,18 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_ugt:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a2, a0
+; RV32-XQCICS-NEXT: sltu a2, a3, a1
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: seqz a1, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a6, a4
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a7, a5
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_ugt:
; RV64: # %bb.0:
; RV64-NEXT: bltu a1, a0, .LBB16_2
@@ -835,6 +960,18 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_uge:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a0, a2
+; RV32-XQCICS-NEXT: sltu a2, a1, a3
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: seqz a1, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_uge:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a0, a1, .LBB17_2
@@ -896,6 +1033,18 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_ult:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a0, a2
+; RV32-XQCICS-NEXT: sltu a2, a1, a3
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: seqz a1, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a6, a4
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a7, a5
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_ult:
; RV64: # %bb.0:
; RV64-NEXT: bltu a0, a1, .LBB18_2
@@ -957,6 +1106,18 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_ule:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a2, a0
+; RV32-XQCICS-NEXT: sltu a2, a3, a1
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: seqz a1, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_ule:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a1, a0, .LBB19_2
@@ -1018,6 +1179,18 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_sgt:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a2, a0
+; RV32-XQCICS-NEXT: slt a2, a3, a1
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: seqz a1, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a6, a4
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a7, a5
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_sgt:
; RV64: # %bb.0:
; RV64-NEXT: blt a1, a0, .LBB20_2
@@ -1079,6 +1252,18 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_sge:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a0, a2
+; RV32-XQCICS-NEXT: slt a2, a1, a3
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: seqz a1, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_sge:
; RV64: # %bb.0:
; RV64-NEXT: bge a0, a1, .LBB21_2
@@ -1140,6 +1325,18 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_slt:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a0, a2
+; RV32-XQCICS-NEXT: slt a2, a1, a3
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: seqz a1, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a6, a4
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a7, a5
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_slt:
; RV64: # %bb.0:
; RV64-NEXT: blt a0, a1, .LBB22_2
@@ -1201,6 +1398,18 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
+; RV32-XQCICS-LABEL: select_i64_sle:
+; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu a0, a2, a0
+; RV32-XQCICS-NEXT: slt a2, a3, a1
+; RV32-XQCICS-NEXT: xor a1, a1, a3
+; RV32-XQCICS-NEXT: seqz a1, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: mv a0, a1
+; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: ret
+;
; RV64-LABEL: select_i64_sle:
; RV64: # %bb.0:
; RV64-NEXT: bge a1, a0, .LBB23_2
>From 5359a689e553650ac17b4ab58eca3fce4d7df58f Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Thu, 3 Jul 2025 10:46:20 +0530
Subject: [PATCH 5/7] fixup! Add comment to justify AddedComplexity
Change-Id: I79661099b5d5aae89a047279f47463f120cfbc2e
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 3d582c38d8277..8fb2d602f1d35 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1489,6 +1489,8 @@ let Predicates = [HasVendorXqcics, IsRV32] in {
def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2),(XLenVT GPRNoX0:$rs3)),
(QC_SELECTEQI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs3, GPRNoX0:$rs2)>;
+// Below AddedComplexity is added to prefer these conditional select instructions over
+// conditional move instructions
let AddedComplexity = 1 in {
def : QCISELECTCCIPat <SETEQ, QC_SELECTEQI>;
def : QCISELECTCCIPat <SETNE, QC_SELECTNEI>;
>From 840a11565e0e27f0cc0b4f465b4b8da31d18bad5 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Tue, 8 Jul 2025 11:02:53 +0530
Subject: [PATCH 6/7] fixup! Add RUN line for testing Xqcicm and Xqcics
together
Change-Id: I3da7ecb9e89b6377d9689678ba39accfeb06a3fa
---
llvm/test/CodeGen/RISCV/xqcics.ll | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index c0c07a9329179..984694ed783e5 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -4,6 +4,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics,+experimental-xqcicm -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq:
>From 06eb3fcbb37497e751d1f7373fecc4868faf6068 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Thu, 10 Jul 2025 13:06:58 +0530
Subject: [PATCH 7/7] fixup! Address comments
Change-Id: I7a7abd76124b0d3a6ab744c4c5c80b007ac1d2f9
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 6 +-
llvm/test/CodeGen/RISCV/select-cond.ll | 96 ++++++-------
llvm/test/CodeGen/RISCV/xqcics.ll | 141 +++++++++++++++-----
3 files changed, 158 insertions(+), 85 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 8fb2d602f1d35..2364ae42744b1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1487,7 +1487,11 @@ def : QCIMVCCIPat <SETULT, QC_MVLTUI>;
let Predicates = [HasVendorXqcics, IsRV32] in {
def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2),(XLenVT GPRNoX0:$rs3)),
- (QC_SELECTEQI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs3, GPRNoX0:$rs2)>;
+ (QC_SELECTNEI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
+def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2), simm5:$simm2),
+ (QC_SELECTINEI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs2, simm5:$simm2)>;
+def : Pat<(select (XLenVT GPRNoX0:$rd), simm5:$simm2,(XLenVT GPRNoX0:$rs2)),
+ (QC_SELECTIEQI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs2, simm5:$simm2)>;
// Below AddedComplexity is added to prefer these conditional select instructions over
// conditional move instructions
diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll
index 7ece32681baf9..59f4d95f45acc 100644
--- a/llvm/test/CodeGen/RISCV/select-cond.ll
+++ b/llvm/test/CodeGen/RISCV/select-cond.ll
@@ -40,7 +40,7 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32-XQCICS-LABEL: select_i32_trunc:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a0, a0, 1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a1
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_trunc:
@@ -91,7 +91,7 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32-XQCICS-LABEL: select_i32_param:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a0, a0, 1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a1
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_param:
@@ -140,7 +140,7 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: xor a0, a0, a1
; RV32-XQCICS-NEXT: seqz a0, a0
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_eq:
@@ -189,7 +189,7 @@ define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: xor a0, a0, a1
; RV32-XQCICS-NEXT: snez a0, a0
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ne:
@@ -237,7 +237,7 @@ define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-LABEL: select_i32_ugt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ugt:
@@ -285,7 +285,7 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-LABEL: select_i32_uge:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a3
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_uge:
@@ -333,7 +333,7 @@ define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-LABEL: select_i32_ult:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ult:
@@ -381,7 +381,7 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-LABEL: select_i32_ule:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a3
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ule:
@@ -429,7 +429,7 @@ define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-LABEL: select_i32_sgt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sgt:
@@ -477,7 +477,7 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-LABEL: select_i32_sge:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a3
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sge:
@@ -525,7 +525,7 @@ define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-LABEL: select_i32_slt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt a0, a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a2
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_slt:
@@ -573,7 +573,7 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICS-LABEL: select_i32_sle:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt a0, a1, a0
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a2, a3
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sle:
@@ -630,8 +630,8 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a1, a0, 1
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a3
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a2
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a3, a5
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a4
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_trunc:
@@ -689,8 +689,8 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a5, a0, 1
; RV32-XQCICS-NEXT: mv a0, a5
-; RV32-XQCICS-NEXT: qc.selecteqi a5, 0, a4, a2
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a3, a1
+; RV32-XQCICS-NEXT: qc.selectnei a5, 0, a2, a4
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a3
; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
@@ -889,14 +889,14 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_ugt:
; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu t0, a3, a1
; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: sltu a2, a3, a1
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a7, a5
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ugt:
@@ -962,14 +962,14 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_uge:
; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu t0, a1, a3
; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: sltu a2, a1, a3
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_uge:
@@ -1035,14 +1035,14 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_ult:
; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu t0, a1, a3
; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: sltu a2, a1, a3
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a7, a5
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ult:
@@ -1108,14 +1108,14 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_ule:
; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: sltu t0, a3, a1
; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: sltu a2, a3, a1
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ule:
@@ -1181,14 +1181,14 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_sgt:
; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: slt t0, a3, a1
; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: slt a2, a3, a1
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a7, a5
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sgt:
@@ -1254,14 +1254,14 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_sge:
; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: slt t0, a1, a3
; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: slt a2, a1, a3
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sge:
@@ -1327,14 +1327,14 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_slt:
; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: slt t0, a1, a3
; RV32-XQCICS-NEXT: sltu a0, a0, a2
-; RV32-XQCICS-NEXT: slt a2, a1, a3
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a6, a4
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a7, a5
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_slt:
@@ -1400,14 +1400,14 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
;
; RV32-XQCICS-LABEL: select_i64_sle:
; RV32-XQCICS: # %bb.0:
+; RV32-XQCICS-NEXT: slt t0, a3, a1
; RV32-XQCICS-NEXT: sltu a0, a2, a0
-; RV32-XQCICS-NEXT: slt a2, a3, a1
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a2, a0
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
-; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
-; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
+; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
+; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sle:
diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll
index 984694ed783e5..0e90b1fda0ea2 100644
--- a/llvm/test/CodeGen/RISCV/xqcics.ll
+++ b/llvm/test/CodeGen/RISCV/xqcics.ll
@@ -7,14 +7,83 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics,+experimental-xqcicm -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
+define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq_s1:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: andi a1, a0, 1
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: bnez a1, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a0, 12
+; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eq_s1:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: andi a0, a0, 1
+; RV32IXQCICS-NEXT: qc.selectinei a0, 0, a2, 12
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cond_trunc = trunc i32 %a to i1
+ %sel = select i1 %cond_trunc, i32 %x, i32 12
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_eq_s2(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq_s2:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: andi a1, a0, 1
+; RV32I-NEXT: bnez a1, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB1_2:
+; RV32I-NEXT: li a0, 12
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eq_s2:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: andi a0, a0, 1
+; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a2, 12
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cond_trunc = trunc i32 %a to i1
+ %sel = select i1 %cond_trunc, i32 12, i32 %x
+ ret i32 %sel
+}
+
+define i32 @select_cc_example_eq_s3(i32 %a, i32 %b, i32 %x, i32 %y) {
+; RV32I-LABEL: select_cc_example_eq_s3:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: andi a0, a0, 1
+; RV32I-NEXT: bnez a0, .LBB2_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: li a0, 25
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB2_2:
+; RV32I-NEXT: li a0, 12
+; RV32I-NEXT: ret
+;
+; RV32IXQCICS-LABEL: select_cc_example_eq_s3:
+; RV32IXQCICS: # %bb.0: # %entry
+; RV32IXQCICS-NEXT: andi a0, a0, 1
+; RV32IXQCICS-NEXT: li a1, 25
+; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a1, 12
+; RV32IXQCICS-NEXT: ret
+entry:
+ %cond_trunc = trunc i32 %a to i1
+ %sel = select i1 %cond_trunc, i32 12, i32 25
+ ret i32 %sel
+}
+
define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
-; RV32I-NEXT: beq a0, a1, .LBB0_2
+; RV32I-NEXT: beq a0, a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: .LBB0_2: # %entry
+; RV32I-NEXT: .LBB3_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -32,10 +101,10 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq_c:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
-; RV32I-NEXT: beq a0, a1, .LBB1_2
+; RV32I-NEXT: beq a0, a1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: .LBB1_2: # %entry
+; RV32I-NEXT: .LBB4_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -53,10 +122,10 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ne:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
-; RV32I-NEXT: bne a0, a1, .LBB2_2
+; RV32I-NEXT: bne a0, a1, .LBB5_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: .LBB2_2: # %entry
+; RV32I-NEXT: .LBB5_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -74,10 +143,10 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ne_c:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
-; RV32I-NEXT: bne a0, a1, .LBB3_2
+; RV32I-NEXT: bne a0, a1, .LBB6_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: .LBB3_2: # %entry
+; RV32I-NEXT: .LBB6_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -94,10 +163,10 @@ entry:
define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eqi:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: beq a0, a1, .LBB4_2
+; RV32I-NEXT: beq a0, a1, .LBB7_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB4_2: # %entry
+; RV32I-NEXT: .LBB7_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -114,10 +183,10 @@ entry:
define i32 @select_cc_example_eqi_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eqi_c:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: bne a0, a1, .LBB5_2
+; RV32I-NEXT: bne a0, a1, .LBB8_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB5_2: # %entry
+; RV32I-NEXT: .LBB8_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -134,10 +203,10 @@ entry:
define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_nei:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: bne a0, a1, .LBB6_2
+; RV32I-NEXT: bne a0, a1, .LBB9_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB6_2: # %entry
+; RV32I-NEXT: .LBB9_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -154,10 +223,10 @@ entry:
define i32 @select_cc_example_nei_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_nei_c:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: beq a0, a1, .LBB7_2
+; RV32I-NEXT: beq a0, a1, .LBB10_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB7_2: # %entry
+; RV32I-NEXT: .LBB10_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -175,10 +244,10 @@ define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: beq a0, a1, .LBB8_2
+; RV32I-NEXT: beq a0, a1, .LBB11_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB8_2: # %entry
+; RV32I-NEXT: .LBB11_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -196,10 +265,10 @@ define i32 @select_cc_example_ieqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi_c1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: beq a0, a1, .LBB9_2
+; RV32I-NEXT: beq a0, a1, .LBB12_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB9_2: # %entry
+; RV32I-NEXT: .LBB12_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -217,10 +286,10 @@ define i32 @select_cc_example_ieqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi_c2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: bne a0, a1, .LBB10_2
+; RV32I-NEXT: bne a0, a1, .LBB13_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB10_2: # %entry
+; RV32I-NEXT: .LBB13_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -238,10 +307,10 @@ define i32 @select_cc_example_ieqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi_c3:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: bne a0, a1, .LBB11_2
+; RV32I-NEXT: bne a0, a1, .LBB14_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB11_2: # %entry
+; RV32I-NEXT: .LBB14_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -259,10 +328,10 @@ define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: bne a0, a1, .LBB12_2
+; RV32I-NEXT: bne a0, a1, .LBB15_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB12_2: # %entry
+; RV32I-NEXT: .LBB15_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -280,10 +349,10 @@ define i32 @select_cc_example_inei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei_c1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: bne a0, a1, .LBB13_2
+; RV32I-NEXT: bne a0, a1, .LBB16_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB13_2: # %entry
+; RV32I-NEXT: .LBB16_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -301,10 +370,10 @@ define i32 @select_cc_example_inei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei_c2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: beq a0, a1, .LBB14_2
+; RV32I-NEXT: beq a0, a1, .LBB17_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB14_2: # %entry
+; RV32I-NEXT: .LBB17_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -322,10 +391,10 @@ define i32 @select_cc_example_inei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei_c3:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
-; RV32I-NEXT: beq a0, a1, .LBB15_2
+; RV32I-NEXT: beq a0, a1, .LBB18_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
-; RV32I-NEXT: .LBB15_2: # %entry
+; RV32I-NEXT: .LBB18_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
@@ -342,11 +411,11 @@ entry:
define i32 @select_cc_example_eqii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eqii:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: beq a0, a1, .LBB16_2
+; RV32I-NEXT: beq a0, a1, .LBB19_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 11
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB16_2:
+; RV32I-NEXT: .LBB19_2:
; RV32I-NEXT: li a0, 13
; RV32I-NEXT: ret
;
@@ -363,11 +432,11 @@ entry:
define i32 @select_cc_example_neii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_neii:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: bne a0, a1, .LBB17_2
+; RV32I-NEXT: bne a0, a1, .LBB20_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 11
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB17_2:
+; RV32I-NEXT: .LBB20_2:
; RV32I-NEXT: li a0, 13
; RV32I-NEXT: ret
;
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